Abstract: A system may concurrently transport datastreams over the common, differential and phantom modes of pair conductor media. The system may implement the phantom mode transport using the differential of multiple common modes. In multiple conductor pair implementations, multiple phantom modes may share a single return signal route. In some implementations, usage of common modes and phantom modes may be paired with schemes to increase signal robustness.

Abstract: A system may concurrently transport datastreams over the common, differential and phantom modes of pair conductor media. The system may implement the phantom mode transport using the differential of multiple common modes. In multiple conductor pair implementations, multiple phantom modes may share a single return signal route. In some implementations, usage of common modes and phantom modes may be paired with schemes to increase signal robustness.

Abstract: A device includes circuitry configured to transmit a first test signal to another device via one or more communication links. The device receives a second test signal transmitted from the another device via the one or more communication links. The circuitry is configured to determine a signal-to-noise ratio (SNR) at the device and the another device. Data rates are determined for the one or more communication links based on the SNR at the device and the another device.

Abstract: Transceiver architecture includes circuitry and a method to transmit and receive high speed WAP data over lower speed cabling such as Cat5e. The method begins by measuring quality of a wired bi-directional communications channel. The method continues by selecting a maximum possible data transmission rate over the wired bi-directional communications channel for the measured quality level and when the maximum possible data transmission rate is a reduced data transmission rate less than a maximum data transmission rate of the transceivers, proportionally adjusting clock rates of circuit elements of the first and second transceiver to transfer the data at the reduced data transmission rate. The method includes dividing data frames of the data to be transmitted N times, where N=number of layers of at least a portion of identical transceiver processing circuitry which is connected to twisted wiring pairs of the wired bi-directional communications channel.

Abstract: Transceiver architecture includes circuitry and a method to transmit and receive high speed WAP data over lower speed cabling such as Cat5e. The method begins by measuring quality of a wired bi-directional communications channel. The method continues by selecting a maximum possible data transmission rate over the wired bi-directional communications channel for the measured quality level and when the maximum possible data transmission rate is a reduced data transmission rate less than a maximum data transmission rate of the transceivers, proportionally adjusting clock rates of circuit elements of the first and second transceiver to transfer the data at the reduced data transmission rate. The method includes dividing data frames of the data to be transmitted N times, where N=number of layers of at least a portion of identical transceiver processing circuitry which is connected to twisted wiring pairs of the wired bi-directional communications channel.

Abstract: Aspects of a method and system for interference cancellation substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. In this regard, a receiver may be operable to receive a differential signal via a differential channel, and to sense a common mode signal on the differential channel. A frequency range in which interference is present in the common mode signal may be determined. The differential signal and the common mode signal may be filtered to attenuate frequencies outside the determined frequency range. A phase and/or amplitude of the filtered common mode signal may be adjusted based on the filtered differential signal and the adjusted and filtered common mode signal may be subtracted from the received differential signal. The common mode signal may be sensed via a pair of resistors coupled to the differential channel.

Abstract: Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients.

Abstract: Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients.

Abstract: Aspects of a method and system for interference cancellation substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. In this regard, a receiver may be operable to receive a differential signal via a differential channel, and to sense a common mode signal on the differential channel. A frequency range in which interference is present in the common mode signal may be determined. The differential signal and the common mode signal may be filtered to attenuate frequencies outside the determined frequency range. A phase and/or amplitude of the filtered common mode signal may be adjusted based on the filtered differential signal and the adjusted and filtered common mode signal may be subtracted from the received differential signal. The common mode signal may be sensed via a pair of resistors coupled to the differential channel.

Abstract: Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients.

Abstract: Aspects of a method and system for adaptive tone cancellation for mitigating the effects of interference are provided. In this regard, an Ethernet PHY may receive one or more signals via a corresponding one or more physical channels and generate one or more estimate signals, each of which approximates interference present in a corresponding one of the received signals. The Ethernet PHY may subtract each one of the estimate signals from a corresponding one of the received signals. The subtracting may occur at the input of one or more slicers in the Ethernet PHY. The received signals may be processed via one or more equalizers in the Ethernet PHY. A decision output of a slicer in the Ethernet PHY may be subtracted from one of the the one or more received signals, and a signal resulting from the subtraction may be utilized to generate the one or more estimate signals.

Abstract: Aspects of a method and system for interference cancellation substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. In this regard, a receiver may be operable to receive a differential signal via a differential channel, and to sense a common mode signal on the differential channel. A frequency range in which interference is present in the common mode signal may be determined. The differential signal and the common mode signal may be filtered to attenuate frequencies outside the determined frequency range. A phase and/or amplitude of the filtered common mode signal may be adjusted based on the filtered differential signal and the adjusted and filtered common mode signal may be subtracted from the received differential signal. The common mode signal may be sensed via a pair of resistors coupled to the differential channel.

Abstract: Aspects of a method and system for adaptive tone cancellation for mitigating the effects of interference are provided. In this regard, an Ethernet PHY may receive one or more signals via a corresponding one or more physical channels and generate one or more estimate signals, each of which approximates interference present in a corresponding one of the received signals. The Ethernet PHY may subtract each one of the estimate signals from a corresponding one of the received signals. The subtracting may occur at the input of one or more slicers in the Ethernet PHY. The received signals may be processed via one or more equalizers in the Ethernet PHY. A decision output of a slicer in the Ethernet PHY may be subtracted from one of the said one or more received signals, and a signal resulting from the subtraction may be utilized to generate the one or more estimate signals.

Abstract: Aspects of a method and system for adaptive tone cancellation for mitigating the effects of interference are provided. In this regard, an Ethernet PHY may receive one or more signals via a corresponding one or more physical channels and generate one or more estimate signals, each of which approximates interference present in a corresponding one of the received signals. The Ethernet PHY may subtract each one of the estimate signals from a corresponding one of the received signals. The subtracting may occur at the input of one or more slicers in the Ethernet PHY. The received signals may be processed via one or more equalizers in the Ethernet PHY. A decision output of a slicer in the Ethernet PHY may be subtracted from one of the said one or more received signals, and a signal resulting from the subtraction may be utilized to generate the one or more estimate signals.

Abstract: Herein described are at least a method and a system for implementing a high speed Tomlinson-Harashima Precoder. The method comprises using an L-tap transpose configuration of a Tomlinson-Harashima Precoder and processing a first discrete time sampled sequence using said L coefficients and L state variables by clocking the L-tap Tomlinson-Harashima Precoder using a clock signal wherein the clock signal has a clock rate equal to one half the symbol rate of the discrete time sampled sequence. In a representative embodiment, an L-tap Tomlinson-Harashima Precoder comprises a single integrated circuit chip, wherein the integrated circuit chip comprises at least one circuitry for processing a discrete time sampled sequence using L coefficients and L state variables by way of clocking the discrete time sampled sequence using a clock signal having a clock rate that is one half the symbol rate of the discrete time sampled sequence.

Abstract: Aspects of a method and system for interference cancellation substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. In this regard, a receiver may be operable to receive a differential signal via a differential channel, and to sense a common mode signal on the differential channel. A frequency range in which interference is present in the common mode signal may be determined. The differential signal and the common mode signal may be filtered to attenuate frequencies outside the determined frequency range. A phase and/or amplitude of the filtered common mode signal may be adjusted based on the filtered differential signal and the adjusted and filtered common mode signal may be subtracted from the received differential signal. The common mode signal may be sensed via a pair of resistors coupled to the differential channel.

Abstract: Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients.

Abstract: Herein described are at least a method and a system for implementing a high speed Tomlinson-Harashima Precoder. The method comprises using an L-tap transpose configuration of a Tomlinson-Harashima Precoder and processing a first discrete time sampled sequence using said L coefficients and L state variables by clocking the L-tap Tomlinson-Harashima Precoder using a clock signal wherein the clock signal has a clock rate equal to one half the symbol rate of the discrete time sampled sequence. In a representative embodiment, an L-tap Tomlinson-Harashima Precoder comprises a single integrated circuit chip, wherein the integrated circuit chip comprises at least one circuitry for processing a discrete time sampled sequence using L coefficients and L state variables by way of clocking the discrete time sampled sequence using a clock signal having a clock rate that is one half the symbol rate of the discrete time sampled sequence.

Abstract: Multi-channel line interface unit with on-chip clock management. A method for clocking a multi-channel Line Interface Unit (LIU) embodied in an integrated circuit and having a plurality of channels is disclosed. Each channel has a receive path and a transmit path. An reference clock input is provided for receiving an external reference clock signal. A free running on-chip clock is generated that is synchronized to the reference clock signal. On at least two of the channels, transmit or receive data clocks and associated corresponding transmit and receive data operating at an associated data rate are received. Transmit and receive data are processed on each of the respective channels with a portion of the processing occurring in the digital domain.