Patents by Inventor Kishore Kumar Muchherla

Kishore Kumar Muchherla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11587639
    Abstract: A voltage calibration scan is initiated. A first value of a data state metric measured for a sample block of a memory device based on associated with a first bin of blocks designated as a current is received. The first value is designated as a minimum value. A second value of the data state metric for the sample block is measured based on a set of read voltage offsets associated with a second bin of blocks having an index value higher than the current bin. In response to determining that the second value exceeds the first value, the first bin is maintained as the current bin and the voltage calibration scan is stopped.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: February 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Xiangang Luo, Peter Feeley, Devin M. Batutis, Jiangang Wu, Sampath K Ratnam, Shane Nowell, Karl D. Schuh
  • Publication number: 20230046724
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing, on data residing in a block of the memory device, an error-handling operation of a plurality of error-handling operations, wherein an order of the plurality of error-handling operations is based on a voltage offset bin associated with the block, wherein the voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations; and responsive to determining that the error-handling operation has failed to recover the data, adjusting the order of the plurality of error-handling operations.
    Type: Application
    Filed: November 2, 2022
    Publication date: February 16, 2023
    Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy, Devin M. Batutis, Xiangang Luo
  • Patent number: 11573720
    Abstract: A includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to: initialize a block family associated with the memory device; initialize a timer at initialization of the block family; and aggregate temperature values received from sensor(s) of the memory device over time to generate an aggregate temperature. Responsive to programming a page residing on the memory device, the processing device associates the page with the block family. The processing device closes the block family in response to the aggregate temperature being greater than a first temperature value and the timer reaching a first time value. The processing device closes the block family in response to the aggregate temperature being less than or equal to the first temperature value and the timer reaching a second time value that is greater than the first time value.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: February 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Larry J. Koudele, Bruce A. Liikanen, Steven Michael Kientz, Kishore Kumar Muchherla
  • Patent number: 11561722
    Abstract: A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device, to store host data in the page of the data unit. The processing device further generates a parity page for the host data stored in the page of the data unit and adds the parity page to parity data stored at a parity data storage location. Responsive to determining that a first size of the stored parity data satisfies a first condition, the processing device initiates execution of a compression algorithm to compress the stored parity data. Responsive to determining that a second size of the parity data resulting from the execution of the compression algorithm satisfies a second condition, the processing device performs a scan operation to release at least a subset of the stored parity data.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Harish R Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla
  • Publication number: 20230012855
    Abstract: A method can include receiving a request to read data from a block of a memory device, identifying a block family associated with the block of the memory device, identifying a voltage distribution parameter value associated with the block family, wherein the voltage distribution parameter value reflects an aggregate value of a corresponding voltage distribution associated with a plurality of memory cells of the block family, and determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device. The block family can be identified using a data structure that maps block identifiers to corresponding block family identifiers. The voltage distribution parameter value can be identified using a data structure that maps block family identifiers to corresponding voltage parameter values.
    Type: Application
    Filed: September 12, 2022
    Publication date: January 19, 2023
    Inventors: Michael Sheperek, Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Larry J. Koudele
  • Publication number: 20230019189
    Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Inventors: Jiangang Wu, Jung Sheng Hoei, Qisong Lin, Kishore Kumar Muchherla
  • Publication number: 20230017591
    Abstract: An initial value of a power cycle count associated with the memory device is identified. The power cycle count is incremented responsive to detecting a powering up of the memory device. Responsive to programming a block residing in the memory device, the block is associated with a current block family associated with the memory device. A currently value of the power cycle count is determined. Responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, the current block family is closed.
    Type: Application
    Filed: September 21, 2022
    Publication date: January 19, 2023
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Peter Feeley, Karl D. Schuh
  • Publication number: 20230012644
    Abstract: A system includes a memory array of sub-blocks, each sub-block including groups of memory cells, and a processing device. The processing device causes a first wordline to be programmed through the sub-blocks with a mask by causing to be programmed, to a first voltage level: a first group of memory cells of a first sub-block; and a second group of memory cells of a second sub-block. The processing device further scans a second wordline that has been programmed and is coupled to the first wordline, scanning includes: causing a custom wordline voltage to be applied to the second wordline, the custom wordline voltage to select groups of memory cells corresponding to those of the first wordline programmed to the first voltage level; concurrently reading data from the selected groups of memory cells of the second wordline; and performing, using the data, an error check of the second wordline.
    Type: Application
    Filed: September 16, 2022
    Publication date: January 19, 2023
    Inventors: Kishore Kumar Muchherla, Violante Moschiano, Sead Zildzic, Junwyn A. Lacsao, Paing Z. Htet
  • Patent number: 11556417
    Abstract: A memory device to use added known data as part of data written to memory cells with redundant data generated according to an Error Correction Code (ECC). The code rate of the ECC may limit its capability to recover from excessive errors in the stored data. To reduce the errors, the added data retrieved from the memory cells can be corrected without using the ECC. Subsequently, remaining errors can be corrected via the ECC. Optionally, the added data can be configured to be the same as the data represented by an erased state of a subset of the memory cells such that when the subset is used to store the added data, the subset remains in the erased state to reduce wearing. Different subsets can be used to store added data for different write operations to distribute the benefit of reduced wearing.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Akira Goda, Mustafa N. Kaynak
  • Patent number: 11557357
    Abstract: An example memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. The time after program is compared to a threshold time level to determine if a first condition is satisfied or a second condition is satisfied. The memory sub-system selects one of a first set of read offset values based on the time after program in response to satisfying the first condition, or a second set of read offset values based on a data state metric measurement in response to satisfying the second condition.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Larry J. Koudele
  • Publication number: 20230005552
    Abstract: A memory system to store multiple bits of data in a memory cell. After receiving the data bits, a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between combinations of bit values and threshold levels. The threshold levels are partitioned into a plurality of groups, each containing a subset of the threshold levels. A group identification of a first group, among the plurality of groups, containing the first level is determined for the memory cell. The memory device reads, using the group identification, a subset of the data bits back from the first memory cell, and combines the bits of the group identification and the subset to recover the entire set of data bits to finely program the threshold voltage of the memory cell to represent the data bits.
    Type: Application
    Filed: September 8, 2022
    Publication date: January 5, 2023
    Inventors: Phong Sy Nguyen, James Fitzpatrick, Kishore Kumar Muchherla
  • Patent number: 11544188
    Abstract: Memory circuits including dynamically configurable cache cells are disclosed herein. The cache cells may be selectively and dynamically configured to select one or more bits per cell according to a real-time determination or characterization of a workload type.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: January 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yun Li, Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam
  • Patent number: 11544008
    Abstract: A memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: January 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Gianni Stephen Alsasua, Karl D. Schuh, Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Sampath Ratnam, Harish Reddy Singidi, Renato Padilla, Jr.
  • Publication number: 20220414021
    Abstract: A first block that is assigned a first sequence identifier can be identified. A determination can be made as to whether the assigned first sequence identifier satisfies a threshold sequence identifier condition that corresponds to a difference between the first sequence identifier assigned to the first block and second sequence identifier assigned to a second block. In response to determining that the assigned first sequence identifier satisfies the threshold sequence identifier condition, a media management operation can be performed on the first block.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Ashutosh Malshe
  • Patent number: 11532373
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an order of a plurality of error-handling operations to be performed to recovery data associated with the read error, wherein the order is specified in a metadata table and is based on the voltage offset bin associated with the block, and performing at least one error-handling operation of the plurality of error-handling operations in the order specified by the metadata table.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: December 20, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy, Devin M. Batutis, Xiangang Luo
  • Patent number: 11527291
    Abstract: A request to perform a secure erase operation for a memory component can be received. A voltage level that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can be associated with a program operation to place a memory cell of the memory component at another voltage level that exceeds the voltage level that is applied to the unselected wordlines of the memory component during the read operation.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: December 13, 2022
    Assignee: MICRON TECHNOLOGY, INC
    Inventors: Kishore Kumar Muchherla, Harish R. Singidi, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Sampath K. Ratnam
  • Publication number: 20220391104
    Abstract: A distribution statistic is generated for a data block of a memory component based on a reliability statistic for memory cells sampled in the data block. The distribution statistic is indicative of at least one of a uniformity or a non-uniformity of read disturb stress on the sampled memory cells. At least a subset of the data block is relocated to another data block of the memory component in view of the distribution statistic.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 8, 2022
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Vamsi Rayaprolu, Harish R. Singidi
  • Publication number: 20220392547
    Abstract: A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.
    Type: Application
    Filed: August 18, 2022
    Publication date: December 8, 2022
    Inventors: Kishore Kumar Muchherla, Karl Schuh, Mustafa N. Kaynak, Xiangang Luo, Shane Nowell, Devin Batutis, Sivagnanam Parthasarathy, Sampath Ratnam, Jiangang Wu, Peter Feeley
  • Publication number: 20220392554
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing a read operation on a block of the memory device by applying a read reference voltage to a selected wordline of the block and applying a pass-through voltage having a first value to a plurality of unselected wordlines of the block; detecting a read error in response to performing the read operation; and setting the pass-through voltage to a second value, wherein the second value is greater than the first value.
    Type: Application
    Filed: August 17, 2022
    Publication date: December 8, 2022
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy
  • Patent number: 11520699
    Abstract: A processing device of a memory sub-system is configured to receive a request to add content to a system data structure, wherein a first plurality of blocks of a common pool of blocks are allocated to the system data structure and a second plurality of blocks of the common pool of blocks are allocated to user data; determine whether user data has been written to the second plurality of blocks of the common pool of blocks within a threshold amount of time; and responsive to determining that the user data has not been written to the second plurality of blocks within the threshold amount of time, allocate a block from the second plurality of blocks of the common pool of blocks allocated to user data to the first plurality of blocks of the common pool of blocks allocated for the system data structure.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: December 6, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Kulachet Tanpairoj, Peter Feeley, Sampath K. Ratnam, Ashutosh Malshe