Abstract: Techniques for the testing of devices are disclosed. A testing environment is accessed. The testing environment includes an instruction RAM, an instruction fetch and decode unit (FAD), a code exerciser, a command interface, and a trace RAM. A device under test (DUT) is accessible by the command interface. The testing environment includes a test instruction set architecture (TISA). A test sequence is programmed by a user. The test sequence includes one or more instructions from within the TISA. The test sequence is stored in the instruction RAM. A first instruction is fetched by the FAD. The fetching includes decoding the first instruction. The first instruction is translated by the code exerciser. The translating produces a first packetized communication, which is sent to the DUT. A first packetized response is received by the command interface from the DUT and is reported to the user.

Abstract: Disclosed embodiments provide techniques for a networking with a network-on-chip (NoC) interface with subtopologies. A system-on-chip (SoC) is accessed. The SoC includes a plurality of logic blocks. A NoC topology is created. The NoC topology includes one or more subtopologies. The one or more subtopologies are based on a physical location of the plurality of logic blocks. Each subtopology includes at least one router. A location of the one or more subtopologies is optimized. The one or more subtopologies are coupled based on one or more communications protocols. A protocol running on the plurality of logic blocks is translated to the one or more communications protocols. Data is sent from a sending subtopology within the one or more subtopologies to a receiving subtopology within the one or more subtopologies.

Abstract: A corrosion detection system includes a wire disposed in a groove extending circumferentially around an exterior surface of a pipe, the pipe comprising a pipe wall and a pipe liner that lines an inside surface of the pipe wall. The corrosion detection system also includes a sensor electrically coupled to the wire. The sensor is configured to generate a voltage in the wire, and detect a change in a property of the wire caused by exposure of the wire to a corrosive fluid that is present within the pipe but outside the pipe liner.

Abstract: Various embodiments for managing uplink transmissions in a mobile communication device may include receiving, on a first subscription of the mobile communication device, an uplink grant from a first network and determining whether a tune-away from the first subscription to a second subscription of the mobile communication device is scheduled to occur during reception of a response message sent from the first network following an initial transmission of a data packet according to the uplink grant. The mobile communication device may use a block error rate and a buffer status report index of a connection between the first subscription and the first network to determine how to manage uplink transmissions following the tune-away.

Abstract: Access terminals are adapted to facilitate power conservation by selectively powering down one or more hardware block when processing a general page message (GPM) received in slotted idle mode. An access terminal may include a processor core, a de-interleaver, a decoder and a firmware block. The firmware block may be adapted to enable the processor core to sleep while the firmware block collects samples of a received transmission and extracts symbols from the collected samples. The firmware block may further power ON the de-interleaver to de-interleave the extracted symbols, and the decoder to decode the de-interleaved symbols. Other aspects, embodiments, and features are also included.

Abstract: A method for calibrating a delay locked loop (“DLL”) having a plurality of delay segments, comprises: determining segment delay values for the delay segments; calculating a full-cycle delay value for an input signal to the DLL; adjusting one or more of the segment delay values as a function of the full-cycle delay value to generate one or more adjusted delay values; and calculating weights for the delay segments as a function of the segment delay values, the full-cycle delay, and the one or more adjusted delay values, wherein the weights are used to calibrate the DLL.

Abstract: A method for calibrating a delay locked loop (“DLL”) having a plurality of delay segments, comprises: determining segment delay values for the delay segments; calculating a full-cycle delay value for an input signal to the DLL; adjusting one or more of the segment delay values as a function of the full-cycle delay value to generate one or more adjusted delay values; and calculating weights for the delay segments as a function of the segment delay values, the full-cycle delay, and the one or more adjusted delay values, wherein the weights are used to calibrate the DLL.

Abstract: The present invention relates to a process for the preparation of carbapenem compound of Formula (I), wherein P1 is hydrogen or a carboxyl protecting group, P3 is hydrogen or a hydroxyl protecting group, R1 is C1-3 alkyl, and A is selected from a group consisting of a) Formula (II), b) Formula (III), c) Formula (IV), d) Formula (V), e) Formula (VI), f) Formula (VII), wherein P2 is hydrogen or an amino protecting group, R2 and R3 may be same or different and are hydrogen, C1-5 alkyl, optionally substituted aryl, or optionally substituted heteroaryl, and X1 is O or S, or its stereoisomers, or salts thereof.

Abstract: Access terminals are adapted to facilitate power conservation by selectively powering down one or more hardware block when processing a general page message (GPM) received in slotted idle mode. An access terminal may include a processor core, a de-interleaver, a decoder and a firmware block. The firmware block may be adapted to enable the processor core to sleep while the firmware block collects samples of a received transmission and extracts symbols from the collected samples. The firmware block may further power ON the de-interleaver to de-interleave the extracted symbols, and the decoder to decode the de-interleaved symbols. Other aspects, embodiments, and features are also included.

Abstract: The present invention relates to a process for the preparation of carbapenem compound of Formula (I), wherein P1 is hydrogen or a carboxyl protecting group, P3 is hydrogen or a hydroxyl protecting group, R1 is C1-3 alkyl, and A is selected from a group consisting of a) Formula (II), b) Formula (III), c) Formula (IV), d) Formula (V), e) Formula (VI), f) Formula (VII), wherein P2 is hydrogen or an amino protecting group, R2 and R3 may be same or different and are hydrogen, C1-5 alkyl, optionally substituted aryl, or optionally substituted heteroaryl, and X1 is O or S, or its stereoisomers, or salts thereof.

Abstract: A method and apparatus for generating identification numbers for PCI Express that provides unique generation and substantially increased system performance. A system having a PCI Express fabric and PCI devices connected thereto generates unique TAG identification numbers for transactions with substantially increased performance. The system generates and prepares up to three available TAG IDs in advance, before a request is granted. When a completion-required request receives a grant, it picks up the TAG ID from the storage rather than generating it on the fly. This enables the system to process back-to-back TLP requests without any dead cycles.

Abstract: A branch of CRC resources is configured to process back-to-back TLPs in a PCIe architecture. A state machine receives back-to-back TLPs and generates carrier signals, which it then routes to the branch of CRC resources. These signals are used to align the back-to-back TLPs such that a LCRC for each of the back-to-back TLPs is calculated by the branch of CRC resources at line speed. The system and method allow substantial gate-count savings to be realized, as the present invention minimizes the number of components necessary to achieve the desired results.

Abstract: A Duty cycle optimized prescaler (10) optimizes the clock duty cycle as close as possible to fifty percent. This is achieved by employing two count by two counters (11,12), one (12)to count negative edges of the clock pulse, and one (11)to count positive edges of the clock pulse. Each counter (11,12) output is connected to a comparator (14,15) which compares each counter output (11,12)to a prescaler setting (13). The comparators (14,15) outputs are input to an OR gate (16), the output of which, when, a logic 1, resets the counters(11,12) and toggles a flip-flop circuit (17) providing a clock output signal.