Abstract: A system includes a data storage device and a host computing device. The data storage device includes a host interface; integrated circuit memory cells; and a processing device. The processing device is configured to execute firmware to perform operations requested by commands received via the host interface and maintenance operations identified by the processing device independent of commands received via the host interface. The host computing device is coupled to the host interface to provide commands with addresses to access the integrated circuit memory cells according to the address. In response to a request, the host computing device is configured to reduce, to below a threshold, a rate of transmitting to the host interface commands to access integrated circuit memory cells; and power up the data storage device to cause the data storage device to perform the maintenance operations.

Abstract: Disclosed are devices and methods for periodically powering up a storage device(s) (SSDs) associated with a vehicle to avoid and prevent data loss. The disclosed embodiments provide mechanisms for preserving stored data collected during the running of a vehicle without requiring the main power supply to be routed through the CPU. Through the improved configuration and application of the disclosed power management integrated circuitry (PMIC), storage devices of a vehicle are enabled to be provided direct power and refreshed without powering on the vehicle (e.g., starting the car). The PMIC also ensures that the necessary power can be provided to and maintained to the storage device(s) in the event of an unexpected power loss.

Abstract: A system includes a data storage device and a host computing device. The data storage device includes a host interface; integrated circuit memory cells; and a processing device. The processing device is configured to execute firmware to perform operations requested by commands received via the host interface and maintenance operations identified by the processing device independent of commands received via the host interface. The host computing device is coupled to the host interface to provide commands with addresses to access the integrated circuit memory cells according to the address. In response to a request, the host computing device is configured to reduce, to below a threshold, a rate of transmitting to the host interface commands to access integrated circuit memory cells; and power up the data storage device to cause the data storage device to perform the maintenance operations.

Abstract: A system includes a data storage device and a host computing device. The data storage device includes a host interface; integrated circuit memory cells; and a processing device. The processing device is configured to execute firmware to perform operations requested by commands received via the host interface and maintenance operations identified by the processing device independent of commands received via the host interface. The host computing device is coupled to the host interface to provide commands with addresses to access the integrated circuit memory cells according to the address. In response to a request, the host computing device is configured to reduce, to below a threshold, a rate of transmitting to the host interface commands to access integrated circuit memory cells; and power up the data storage device to cause the data storage device to perform the maintenance operations.

Abstract: A system includes a data storage device and a host computing device. The data storage device includes a host interface; integrated circuit memory cells; and a processing device. The processing device is configured to execute firmware to perform operations requested by commands received via the host interface and maintenance operations identified by the processing device independent of commands received via the host interface. The host computing device is coupled to the host interface to provide commands with addresses to access the integrated circuit memory cells according to the address. In response to a request, the host computing device is configured to reduce, to below a threshold, a rate of transmitting to the host interface commands to access integrated circuit memory cells; and power up the data storage device to cause the data storage device to perform the maintenance operations.

Abstract: Disclosed are devices and methods for periodically powering up a storage device(s) (SSDs) associated with a vehicle to avoid and prevent data loss. The disclosed embodiments provide mechanisms for preserving stored data collected during the running of a vehicle without requiring the main power supply to be routed through the CPU. Through the improved configuration and application of the disclosed power management integrated circuitry (PMIC), storage devices of a vehicle are enabled to be provided direct power and refreshed without powering on the vehicle (e.g., starting the car). The PMIC also ensures that the necessary power can be provided to and maintained to the storage device(s) in the event of an unexpected power loss.

Abstract: A method and system for augmenting routing decisions in a network switching device with topology information acquired using source learning are disclosed. In the preferred embodiment, the method of selecting a port to transmit an outbound flow from a first node to a second node comprises the steps of identifying a plurality of ports associated with minimal equal-cost paths from the first node to the second node, and if an inbound flow from the second node is detected on a first port of the plurality of ports of the first node, then transmitting the outbound flow from the first port. In the absence of an inbound flow from the second node, the first node generally selects the port for the outbound flow from the plurality of minimal equal-cost paths.

Abstract: A system and apparatus for controlling a burst sequence in a synchronous memory is described. In one embodiment, the system comprises a synchronous memory and a burst read device coupled to the synchronous memory. In one embodiment, the burst read device is configured to sense a page of data as a current page from the synchronous memory, wherein the current page contains a fixed number of words of data. The device is further configured to latch the current page of data, and synchronously read the current page of data, one word at a time. In an alternate embodiment, the burst read device further comprises a wrap-bit. If the wrap-bit is not set, the burst read device is configured to latch the current page of data, adjust a word pointer to indicate a next word of data, and repeat latching and adjusting in a sequential burst read order.