Patents by Inventor Kishore SINGH
Kishore SINGH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972295Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating customized recommendations for environmentally-conscious cloud computing frameworks for replacing computing resources of existing datacenters. One of the methods involves receiving, through a user interface presented on a display of a computing device, data regarding a user's existing datacenter deployment and the user's preferences for the new cloud computing framework, generating one or more recommendations for environmentally-conscious cloud computing frameworks based on the received data, and presenting such recommendations through the user interface for the user's review and consideration.Type: GrantFiled: October 24, 2022Date of Patent: April 30, 2024Assignee: Accenture Global Solutions LimitedInventors: Vibhu Sharma, Vikrant Kaulgud, Mainak Basu, Sanjay Podder, Kishore P. Durg, Sundeep Singh, Rajan Dilavar Mithani, Akshay Kasera, Swati Sharma, Priyavanshi Pathania, Adam Patten Burden, Pavel Valerievich Ponomarev, Peter Michael Lacy, Joshy Ravindran
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Publication number: 20240126718Abstract: In some embodiments, apparatuses and methods are provided herein useful to validating migrated data. In some embodiments, there is provided a system for validating migrated data including a control circuit configured to migrate data from a first database platform to a second database platform and validate the migrated data. The control circuit configured to transmit a message indicating a mismatch in response to a determination that a first single aggregated hash value does not match with a second single aggregated hash value.Type: ApplicationFiled: October 12, 2022Publication date: April 18, 2024Inventors: Susarla Sitarama S Chakravarthy, Ankit Singh, Pranabh Kumar Thaduri, Kishore Tupili, James T. Motter
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Patent number: 10957703Abstract: An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first and second locations for first and second NVM cells. A common charge trapping layer is formed as a continuous structure over the substrate, where a first portion of the charge trapping layer is disposed directly over the isolation structure and second portions of the charge trapping layer are disposed directly over the first and second substrate locations. Nitrogen doping of the first portion of the charge trapping layer is performed, where after the nitrogen doping is performed the first portion of the charge trapping layer includes a higher nitrogen concentration than the second portions. The first and second NVM cells are then formed over the first and second substrate locations, where the first and second NVM cells include the second portions of the charge trapping layer.Type: GrantFiled: August 6, 2018Date of Patent: March 23, 2021Assignee: Cypress Semiconductor CorporationInventors: Pawan Kishore Singh, Shivananda Shetty, James Pak
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Publication number: 20190074286Abstract: An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first and second locations for first and second NVM cells. A common charge trapping layer is formed as a continuous structure over the substrate, where a first portion of the charge trapping layer is disposed directly over the isolation structure and second portions of the charge trapping layer are disposed directly over the first and second substrate locations. Nitrogen doping of the first portion of the charge trapping layer is performed, where after the nitrogen doping is performed the first portion of the charge trapping layer includes a higher nitrogen concentration than the second portions. The first and second NVM cells are then formed over the first and second substrate locations, where the first and second NVM cells include the second portions of the charge trapping layer.Type: ApplicationFiled: August 6, 2018Publication date: March 7, 2019Applicant: Cypress Semiconductor CorporationInventors: Pawan Kishore Singh, Shivananda Shetty, James Pak
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Patent number: 10068912Abstract: A memory apparatus that has at least two non-volatile memory (NVM) cells disposed side by side overlying a substrate and an isolation structure disposed between the first and second NVM cells in the substrate. The first and second NVM cells share a common charge trapping layer that includes a continuous structure, and the portion of the common charge trapping layer that is disposed directly above the isolation structure includes a higher oxygen and/or nitrogen concentration than the portions of the common charge trapping layer that are disposed within the first and second NVM cells.Type: GrantFiled: June 5, 2017Date of Patent: September 4, 2018Assignee: Cypress Semiconductor CorporationInventors: Pawan Kishore Singh, Shivananda Shetty, James Pak
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Publication number: 20160009603Abstract: A urea-based slow-release fertilizer composition comprising an alkaline oil component and a urea component, wherein, the alkaline oil component is coated on the urea component, such that the ratio of the alkaline oil component to the urea component is in the range of 0.01:100 to 0.1:100. The fertilizer is cost-effective, easy-to-use, and its quality is maintained during storage and transport.Type: ApplicationFiled: November 28, 2011Publication date: January 14, 2016Applicants: Aditya Birla Nuvo Limited, Aditya Birla Science And Technology Co. Ltd.Inventors: Prashant Micky PURI, Kishore SINGH, Anand Kumar SRIVASTAVA, Anand Kishore GUPTA, Sanjaya MOHAPATRA
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Patent number: 8582962Abstract: A thermal processing chamber with a dielectric barrier discharge (DBD) lamp assembly and a method for using the same are provided. In one embodiment, a thermal processing chamber includes a chamber body and a dielectric barrier discharge lamp assembly. The dielectric barrier discharge lamp assembly further comprises a first electrode, a second electrode and a dielectric barrier. The dielectric barrier discharge lamp assembly is positioned between the first electrode and the second electrode. The dielectric barrier defines a discharge space between the dielectric barrier and the second electrode. A circuit arrangement is coupled to the first and second electrodes, and is adapted to operate the dielectric barrier discharge lamp assembly.Type: GrantFiled: July 1, 2011Date of Patent: November 12, 2013Assignee: Applied Materials, Inc.Inventors: Joseph Michael Ranish, Kaushal Kishore Singh, Bruce Adams
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Publication number: 20110263138Abstract: A thermal processing chamber with a dielectric barrier discharge (DBD) lamp assembly and a method for using the same are provided. In one embodiment, a thermal processing chamber includes a chamber body and a dielectric barrier discharge lamp assembly. The dielectric barrier discharge lamp assembly further comprises a first electrode, a second electrode and a dielectric barrier. The dielectric barrier discharge lamp assembly is positioned between the first electrode and the second electrode. The dielectric barrier defines a discharge space between the dielectric barrier and the second electrode. A circuit arrangement is coupled to the first and second electrodes, and is adapted to operate the dielectric barrier discharge lamp assembly.Type: ApplicationFiled: July 1, 2011Publication date: October 27, 2011Inventors: Joseph Michael Ranish, Kaushal Kishore Singh, Bruce Adams
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Patent number: 7978964Abstract: A thermal processing chamber with a dielectric barrier discharge (DBD) lamp assembly and a method for using the same are provided. In one embodiment, a thermal processing chamber includes a chamber body and a dielectric barrier discharge lamp assembly. The dielectric barrier discharge lamp assembly further comprises a first electrode, a second electrode and a dielectric barrier. The dielectric barrier discharge lamp assembly is positioned between the first electrode and the second electrode. The dielectric barrier defines a discharge space between the dielectric barrier and the second electrode. A circuit arrangement is coupled to the first and second electrodes, and is adapted to operate the dielectric barrier discharge lamp assembly.Type: GrantFiled: April 27, 2006Date of Patent: July 12, 2011Assignee: Applied Materials, Inc.Inventors: Joseph Michael Ranish, Kaushal Kishore Singh, Bruce Adams
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Publication number: 20020075631Abstract: The present invention provides a capacitor having upper and lower electrodes formed of iridium or iridium oxide or combinations thereof. The electrodes are preferably formed using physical vapor deposition. An insulating layer disposed between the electrodes can be a ferroelectric ceramic such as PZT or PLZT.Type: ApplicationFiled: December 27, 2000Publication date: June 20, 2002Applicant: Applied Materials, Inc.Inventors: Kaushal Kishore Singh, Farid Abooameri, Visweswaren Sivaramakrishnan, Talex Sajoto, Vicente Lim, Jun Zhao
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Patent number: 6366567Abstract: A first device detects whether a second device implements full duplex communication. When the first device begins receiving a network packet from the second device, the first device transmits a jam signal to the second device. When transmission of the network packet from the second device to the first device has been completed, the first device determines whether a check value within the network packet is valid. When the check value is valid, the first device recognizes that the second device implements full duplex communication. When the check value is not valid, the first device recognizes that the second device does not implement full duplex communication.Type: GrantFiled: August 6, 1998Date of Patent: April 2, 2002Assignee: Hewlett-Packard CompanyInventors: Bharat Kishore Singh, Bruce Anthony Klemin, Michael Richard James