Patents by Inventor Kishore SINGH
Kishore SINGH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11610046Abstract: A document authoring application receives a text input including one or more alphanumeric characters. A glyph extraction module in the application determines graphical data describing glyphs of the alphanumeric characters. From the graphical data, the glyph extraction module extracts visual elements, each visual element including a color or an outline from the glyphs. The glyph extraction module generates a responsive font effect that includes the extracted visual element applied to one or more of an underline effect, a strikethrough effect, a bullet point effect, or a list dot effect. Responsive to a modification of the text input, the glyph extraction module extracts an additional visual element from an additional glyph associated with the modified text. The responsive font effect is modified to include the additional visual element. The user interface is updated to display the responsive font effect or the modified font effect.Type: GrantFiled: October 29, 2019Date of Patent: March 21, 2023Assignee: Adobe Inc.Inventors: Pawan Kishor Singh, Nirmal Kumawat, Saikat Chakrabarty
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Patent number: 11367231Abstract: Systems and methods provide snap-line generation operations for live multi-path glyphs. In this regard, an attribute extraction component accesses a glyph description of a live multi-path glyph to determine and store several attributes related to at least one sub-path of the live multi-path glyph. The stored attributes are accessed by a snap-line generation component and used to determine whether an external object is moved near the live multi-path glyph. When moved near one another, a snap-line is generated along sub-path planes of the external object and the live multi-path glyph. Generated snap-lines are used to aid a user in aligning the two objects.Type: GrantFiled: October 22, 2020Date of Patent: June 21, 2022Assignee: Adobe Inc.Inventors: Nirmal Kumawat, Pawan Kishor Singh
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Publication number: 20220130085Abstract: Systems and methods provide snap-line generation operations for live multi-path glyphs. In this regard, an attribute extraction component accesses a glyph description of a live multi-path glyph to determine and store several attributes related to at least one sub-path of the live multi-path glyph. The stored attributes are accessed by a snap-line generation component and used to determine whether an external object is moved near the live multi-path glyph. When moved near one another, a snap-line is generated along sub-path planes of the external object and the live multi-path glyph. Generated snap-lines are used to aid a user in aligning the two objects.Type: ApplicationFiled: October 22, 2020Publication date: April 28, 2022Inventors: Nirmal Kumawat, Pawan Kishor Singh
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Publication number: 20220089523Abstract: The present invention disclosed 3-substituted phenylamidine compounds of general formula (I), wherein R1, R2, R3, R4, R4a, R4b, A and E have the same meanings as defined in description. The present invention further discloses methods for their preparation and use of the compounds of general formula (I) as a crop protection agent.Type: ApplicationFiled: January 13, 2020Publication date: March 24, 2022Applicant: PI INDUSTRIES LTD.Inventors: Maruti NAIK, Vishal A. MAHAJAN, S. SIVAKUMAR, Kishor Singh RATHOD, Sachin Nagnath GUMME, Santosh Shridhar AUTKAR, Ruchi GARG, Hagalavadi M VENKATESHA, Alexander G.M. KLAUSENER
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Publication number: 20210124796Abstract: A document authoring application receives a text input including one or more alphanumeric characters. A glyph extraction module in the application determines graphical data describing glyphs of the alphanumeric characters. From the graphical data, the glyph extraction module extracts visual elements, each visual element including a color or an outline from the glyphs. The glyph extraction module generates a responsive font effect that includes the extracted visual element applied to one or more of an underline effect, a strikethrough effect, a bullet point effect, or a list dot effect. Responsive to a modification of the text input, the glyph extraction module extracts an additional visual element from an additional glyph associated with the modified text. The responsive font effect is modified to include the additional visual element. The user interface is updated to display the responsive font effect or the modified font effect.Type: ApplicationFiled: October 29, 2019Publication date: April 29, 2021Inventors: Pawan Kishor Singh, Nirmal Kumawat, Saikat Chakrabarty
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Patent number: 10957703Abstract: An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first and second locations for first and second NVM cells. A common charge trapping layer is formed as a continuous structure over the substrate, where a first portion of the charge trapping layer is disposed directly over the isolation structure and second portions of the charge trapping layer are disposed directly over the first and second substrate locations. Nitrogen doping of the first portion of the charge trapping layer is performed, where after the nitrogen doping is performed the first portion of the charge trapping layer includes a higher nitrogen concentration than the second portions. The first and second NVM cells are then formed over the first and second substrate locations, where the first and second NVM cells include the second portions of the charge trapping layer.Type: GrantFiled: August 6, 2018Date of Patent: March 23, 2021Assignee: Cypress Semiconductor CorporationInventors: Pawan Kishore Singh, Shivananda Shetty, James Pak
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Publication number: 20210064906Abstract: A glyph-aware method for underlining text in digital typography includes identifying first and second intersection coordinates where first and second bounds of an underline region of the text intersect with an outline path of a glyph in the text. Where such intersections occur, a portion of the outline path of the glyph between the first and second intersection coordinates is copied. First and second offset coordinates for the underline are determined by adding or subtracting an offset to the first and second intersection coordinates. A first underline outline path is constructed in the underline region, where the first underline outline path includes the copied of the outline path of the glyph between the first and second intersection coordinates. A display device renders an underline, at least partially, along the first underline outline path between the first and second offset coordinates in the underline region of the text.Type: ApplicationFiled: August 30, 2019Publication date: March 4, 2021Applicant: Adobe Inc.Inventors: Pawan Kishor Singh, Nirmal Kumawat
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Patent number: 10922575Abstract: A glyph-aware method for underlining text in digital typography includes identifying first and second intersection coordinates where first and second bounds of an underline region of the text intersect with an outline path of a glyph in the text. Where such intersections occur, a portion of the outline path of the glyph between the first and second intersection coordinates is copied. First and second offset coordinates for the underline are determined by adding or subtracting an offset to the first and second intersection coordinates. A first underline outline path is constructed in the underline region, where the first underline outline path includes the copied of the outline path of the glyph between the first and second intersection coordinates. A display device renders an underline, at least partially, along the first underline outline path between the first and second offset coordinates in the underline region of the text.Type: GrantFiled: August 30, 2019Date of Patent: February 16, 2021Assignee: Adobe Inc.Inventors: Pawan Kishor Singh, Nirmal Kumawat
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Publication number: 20200337311Abstract: The present invention disclosed fluoralkenyl compounds of general formula (I); wherein; R, R1, R2, R3, A and integers n, m and k are as defined in description. The present invention further discloses use of the compounds of general formula (I) to protect crops by controlling or preventing against undesired phytopathogenic microorganisms such as nematodes and phytopathogenic fungi.Type: ApplicationFiled: December 17, 2018Publication date: October 29, 2020Applicant: PI INDUSTRIES LTD.Inventors: Sathishkumar Murugan, Renugadevi Gurusamy, Gopalkrushna Tulshidas Waghule, Suresh Ashamoni, Kishor Singh Rathod, Vikram Singh Jhala, Uzma Khan, Deepak Lahanya Ebhad, Anil Kumar Verma, Ruchi Garg, Hagalavadi M. Venkatesha, Alexander G.M. KLAUSENER
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Publication number: 20190074286Abstract: An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first and second locations for first and second NVM cells. A common charge trapping layer is formed as a continuous structure over the substrate, where a first portion of the charge trapping layer is disposed directly over the isolation structure and second portions of the charge trapping layer are disposed directly over the first and second substrate locations. Nitrogen doping of the first portion of the charge trapping layer is performed, where after the nitrogen doping is performed the first portion of the charge trapping layer includes a higher nitrogen concentration than the second portions. The first and second NVM cells are then formed over the first and second substrate locations, where the first and second NVM cells include the second portions of the charge trapping layer.Type: ApplicationFiled: August 6, 2018Publication date: March 7, 2019Applicant: Cypress Semiconductor CorporationInventors: Pawan Kishore Singh, Shivananda Shetty, James Pak
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Patent number: 10068912Abstract: A memory apparatus that has at least two non-volatile memory (NVM) cells disposed side by side overlying a substrate and an isolation structure disposed between the first and second NVM cells in the substrate. The first and second NVM cells share a common charge trapping layer that includes a continuous structure, and the portion of the common charge trapping layer that is disposed directly above the isolation structure includes a higher oxygen and/or nitrogen concentration than the portions of the common charge trapping layer that are disposed within the first and second NVM cells.Type: GrantFiled: June 5, 2017Date of Patent: September 4, 2018Assignee: Cypress Semiconductor CorporationInventors: Pawan Kishore Singh, Shivananda Shetty, James Pak
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Publication number: 20160009603Abstract: A urea-based slow-release fertilizer composition comprising an alkaline oil component and a urea component, wherein, the alkaline oil component is coated on the urea component, such that the ratio of the alkaline oil component to the urea component is in the range of 0.01:100 to 0.1:100. The fertilizer is cost-effective, easy-to-use, and its quality is maintained during storage and transport.Type: ApplicationFiled: November 28, 2011Publication date: January 14, 2016Applicants: Aditya Birla Nuvo Limited, Aditya Birla Science And Technology Co. Ltd.Inventors: Prashant Micky PURI, Kishore SINGH, Anand Kumar SRIVASTAVA, Anand Kishore GUPTA, Sanjaya MOHAPATRA
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Patent number: 8582962Abstract: A thermal processing chamber with a dielectric barrier discharge (DBD) lamp assembly and a method for using the same are provided. In one embodiment, a thermal processing chamber includes a chamber body and a dielectric barrier discharge lamp assembly. The dielectric barrier discharge lamp assembly further comprises a first electrode, a second electrode and a dielectric barrier. The dielectric barrier discharge lamp assembly is positioned between the first electrode and the second electrode. The dielectric barrier defines a discharge space between the dielectric barrier and the second electrode. A circuit arrangement is coupled to the first and second electrodes, and is adapted to operate the dielectric barrier discharge lamp assembly.Type: GrantFiled: July 1, 2011Date of Patent: November 12, 2013Assignee: Applied Materials, Inc.Inventors: Joseph Michael Ranish, Kaushal Kishore Singh, Bruce Adams
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Publication number: 20110263138Abstract: A thermal processing chamber with a dielectric barrier discharge (DBD) lamp assembly and a method for using the same are provided. In one embodiment, a thermal processing chamber includes a chamber body and a dielectric barrier discharge lamp assembly. The dielectric barrier discharge lamp assembly further comprises a first electrode, a second electrode and a dielectric barrier. The dielectric barrier discharge lamp assembly is positioned between the first electrode and the second electrode. The dielectric barrier defines a discharge space between the dielectric barrier and the second electrode. A circuit arrangement is coupled to the first and second electrodes, and is adapted to operate the dielectric barrier discharge lamp assembly.Type: ApplicationFiled: July 1, 2011Publication date: October 27, 2011Inventors: Joseph Michael Ranish, Kaushal Kishore Singh, Bruce Adams
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Patent number: 7978964Abstract: A thermal processing chamber with a dielectric barrier discharge (DBD) lamp assembly and a method for using the same are provided. In one embodiment, a thermal processing chamber includes a chamber body and a dielectric barrier discharge lamp assembly. The dielectric barrier discharge lamp assembly further comprises a first electrode, a second electrode and a dielectric barrier. The dielectric barrier discharge lamp assembly is positioned between the first electrode and the second electrode. The dielectric barrier defines a discharge space between the dielectric barrier and the second electrode. A circuit arrangement is coupled to the first and second electrodes, and is adapted to operate the dielectric barrier discharge lamp assembly.Type: GrantFiled: April 27, 2006Date of Patent: July 12, 2011Assignee: Applied Materials, Inc.Inventors: Joseph Michael Ranish, Kaushal Kishore Singh, Bruce Adams
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Publication number: 20020075631Abstract: The present invention provides a capacitor having upper and lower electrodes formed of iridium or iridium oxide or combinations thereof. The electrodes are preferably formed using physical vapor deposition. An insulating layer disposed between the electrodes can be a ferroelectric ceramic such as PZT or PLZT.Type: ApplicationFiled: December 27, 2000Publication date: June 20, 2002Applicant: Applied Materials, Inc.Inventors: Kaushal Kishore Singh, Farid Abooameri, Visweswaren Sivaramakrishnan, Talex Sajoto, Vicente Lim, Jun Zhao
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Patent number: 6366567Abstract: A first device detects whether a second device implements full duplex communication. When the first device begins receiving a network packet from the second device, the first device transmits a jam signal to the second device. When transmission of the network packet from the second device to the first device has been completed, the first device determines whether a check value within the network packet is valid. When the check value is valid, the first device recognizes that the second device implements full duplex communication. When the check value is not valid, the first device recognizes that the second device does not implement full duplex communication.Type: GrantFiled: August 6, 1998Date of Patent: April 2, 2002Assignee: Hewlett-Packard CompanyInventors: Bharat Kishore Singh, Bruce Anthony Klemin, Michael Richard James