Patents by Inventor Kishore Ven Kasamsetty
Kishore Ven Kasamsetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180226120Abstract: In one embodiment, a memory device includes a clock receiver to receive a clock signal and a plurality of mode registers to store parameter information associated with a plurality of operating clock frequencies of the clock signal. The plurality of clock frequencies include a first clock frequency and a second clock frequency. The memory device also includes a command interface to receive commands synchronously with respect to the clock signal. The command interface receives a command that instructs the DRAM device to change operation from the first clock frequency to the second clock frequency.Type: ApplicationFiled: December 27, 2017Publication date: August 9, 2018Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Publication number: 20180122444Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.Type: ApplicationFiled: October 30, 2017Publication date: May 3, 2018Inventors: Frederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty
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Patent number: 9886993Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: October 24, 2016Date of Patent: February 6, 2018Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Patent number: 9818463Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.Type: GrantFiled: December 26, 2016Date of Patent: November 14, 2017Assignee: Rambus Inc.Inventors: Frederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty
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Publication number: 20170133070Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.Type: ApplicationFiled: December 26, 2016Publication date: May 11, 2017Inventors: Frederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty
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Publication number: 20170103802Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: ApplicationFiled: October 24, 2016Publication date: April 13, 2017Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Patent number: 9563597Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.Type: GrantFiled: December 20, 2012Date of Patent: February 7, 2017Assignee: Rambus Inc.Inventors: Frederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty
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Patent number: 9502096Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: December 17, 2014Date of Patent: November 22, 2016Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Patent number: 9111645Abstract: Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.Type: GrantFiled: July 17, 2009Date of Patent: August 18, 2015Assignee: Rambus Inc.Inventors: Kishore Ven Kasamsetty, Wayne S. Richardson, Kurt Knorpp, Frederick A. Ware
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Publication number: 20150103610Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: ApplicationFiled: December 17, 2014Publication date: April 16, 2015Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Publication number: 20150089164Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.Type: ApplicationFiled: December 20, 2012Publication date: March 26, 2015Inventors: Frederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty
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Patent number: 8942056Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: February 15, 2012Date of Patent: January 27, 2015Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Publication number: 20130305074Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: ApplicationFiled: February 15, 2012Publication date: November 14, 2013Applicant: RAMBUS INC.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Publication number: 20120011331Abstract: The present embodiments provide a memory system which is configured to send a request from a memory controller to a memory device, wherein the request includes independent activate and precharge commands. The activate command is associated with a row address, which identifies a first row for the activate command. In response to the activate command, the system activates the first row in a first bank in the memory device. Similarly, in response to the precharge command, the system precharges a second bank in the memory device.Type: ApplicationFiled: March 10, 2010Publication date: January 12, 2012Applicant: RAMBUS INC.Inventors: Frederick A. Ware, John Welsford Brooks, Kishore Ven Kasamsetty, Richard E. Perego
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Publication number: 20110126081Abstract: Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.Type: ApplicationFiled: July 17, 2009Publication date: May 26, 2011Applicant: RAMBUS INC.Inventors: Kishore Ven Kasamsetty, Wayne S. Richardson, Kurt Knorpp, Frederick A. Ware