Abstract: A vehicle body reinforcing structure which increases rigidity of a front side member, a shock absorber housing, and a fender apron of a vehicle body may include the fender apron that connects the front side member and the shock absorber housing, and the fender apron that is formed in a pipe shape so that work hardening occurs in a process of manufacturing the pipe-shaped fender apron.

Abstract: A vehicle body reinforcing structure which increases rigidity of a front side member, a shock absorber housing, and a fender apron of a vehicle body may include the fender apron that connects the front side member and the shock absorber housing, and the fender apron that is formed in a pipe shape so that work hardening occurs in a process of manufacturing the pipe-shaped fender apron.

Abstract: A semiconductor device includes a substrate having a via region and a circuit region, an insulation interlayer formed on a top surface of the substrate, a through electrode having a first surface and a second surface, wherein the through electrode penetrates the via region of the substrate and the second surface is substantially coplanar with a bottom surface of the substrate, a first upper wiring formed on a portion of the first surface of the through electrode, a plurality of via contacts formed on a portion of a top surface of the first upper wiring, and a second upper wiring formed on the plurality of via contacts.

Abstract: A wiring structure in a semiconductor device may include a first insulation layer formed on a substrate, a first contact plug, a capping layer pattern, a second insulation layer and a second contact plug. The first insulation layer has a first opening that exposes a contact region of the substrate. The first contact plug is formed on the contact region to partially fill up the first opening. The capping layer pattern is formed on the first contact plug to fill up the first opening. The second insulation layer is formed on the capping layer pattern and the first insulation layer. The second insulation layer has a second opening passing through the capping layer pattern to expose the first contact plug. The second contact plug is formed on the first contact plug in the second opening. Since the wiring structure includes the capping layer pattern, the wiring structure may prevent a contact failure by preventing chemicals from permeating into the first contact plug.

Abstract: A semiconductor device includes a substrate having a via region and a circuit region, an insulation interlayer formed on a top surface of the substrate, a through electrode having a first surface and a second surface, wherein the through electrode penetrates the via region of the substrate and the second surface is substantially coplanar with a bottom surface of the substrate, a first upper wiring formed on a portion of the first surface of the through electrode, a plurality of via contacts formed on a portion of a top surface of the first upper wiring, and a second upper wiring formed on the plurality of via contacts.

Abstract: A wiring structure in a semiconductor device may include a first insulation layer formed on a substrate, a first contact plug, a capping layer pattern, a second insulation layer and a second contact plug. The first insulation layer has a first opening that exposes a contact region of the substrate. The first contact plug is formed on the contact region to partially fill up the first opening. The capping layer pattern is formed on the first contact plug to fill up the first opening. The second insulation layer is formed on the capping layer pattern and the first insulation layer. The second insulation layer has a second opening passing through the capping layer pattern to expose the first contact plug. The second contact plug is formed on the first contact plug in the second opening. Since the wiring structure includes the capping layer pattern, the wiring structure may prevent a contact failure by preventing chemicals from permeating into the first contact plug.

Abstract: A wiring structure in a semiconductor device may include a first insulation layer formed on a substrate, a first contact plug, a capping layer pattern, a second insulation layer and a second contact plug. The first insulation layer has a first opening that exposes a contact region of the substrate. The first contact plug is formed on the contact region to partially fill up the first opening. The capping layer pattern is formed on the first contact plug to fill up the first opening. The second insulation layer is formed on the capping layer pattern and the first insulation layer. The second insulation layer has a second opening passing through the capping layer pattern to expose the first contact plug. The second contact plug is formed on the first contact plug in the second opening. Since the wiring structure includes the capping layer pattern, the wiring structure may prevent a contact failure by preventing chemicals from permeating into the first contact plug.

Abstract: A front structure for a car body that reduces time and cost to repair a car body after a collision by localizing damage in low-speed collisions to a crash box mounted in a space between a front bumper and a side member and making the car body deform always in a predetermined mode in the collisions. A front structure for a car body may include a first connecting bracket supporting the left and right rear of a front bumper, a crash box joined to the rear of the first connecting bracket, a second connecting bracket joined to the rear of the crash box, and a front side member joined to the rear of the second connecting bracket. The crash box includes an inner member and an outer member, which are curved and separated from each other, so as to extend in the longitudinal direction of the vehicle and have a closed cross section. The inner member has a plurality of bead-shaped protrusions that are formed across the inner member and longitudinally spaced from each other.

Abstract: A front structure for a car body that reduces time and cost to repair a car body after a collision by localizing damage in low-speed collisions to a crash box mounted in a space between a front bumper and a side member and making the car body deform always in a predetermined mode in the collisions. A front structure for a car body may include a first connecting bracket supporting the left and right rear of a front bumper, a crash box joined to the rear of the first connecting bracket, a second connecting bracket joined to the rear of the crash box, and a front side member joined to the rear of the second connecting bracket. The crash box includes an inner member and an outer member, which are curved and separated from each other, so as to extend in the longitudinal direction of the vehicle and have a closed cross section. The inner member has a plurality of bead-shaped protrusions that are formed across the inner member and longitudinally spaced from each other.

Abstract: A wiring structure in a semiconductor device may include a first insulation layer formed on a substrate, a first contact plug, a capping layer pattern, a second insulation layer and a second contact plug. The first insulation layer has a first opening that exposes a contact region of the substrate. The first contact plug is formed on the contact region to partially fill up the first opening. The capping layer pattern is formed on the first contact plug to fill up the first opening. The second insulation layer is formed on the capping layer pattern and the first insulation layer. The second insulation layer has a second opening passing through the capping layer pattern to expose the first contact plug. The second contact plug is formed on the first contact plug in the second opening. Since the wiring structure includes the capping layer pattern, the wiring structure may prevent a contact failure by preventing chemicals from permeating into the first contact plug.

Abstract: A semiconductor memory device and a method of manufacturing same, wherein landing pads are formed to contact source/drain regions of an access transistor in a memory cell array area and a first resistor device is formed in the peripheral circuit area, by depositing a first conductive layer on a semiconductor substrate having an access transistor formed thereon and patterning the first conductive layer. An interlayer insulation layer is deposited on the resultant structure, and a lower electrode and a dielectric layer having a high dielectric constant of a capacitor are formed to contact the source/drain region of the access transistor. By depositing a second conductive layer on the resultant structure having the dielectric layer and patterning the dielectric layer, a capacitor upper electrode is formed in the memory cell array area and a second resistor device is formed in the peripheral circuit area.

Abstract: A semiconductor memory device and a method of manufacturing same, wherein landing pads are formed to contact source/drain regions of an access transistor in a memory cell array area and a first resistor device is formed in the peripheral circuit area, by depositing a first conductive layer on a semiconductor substrate having an access transistor formed thereon and patterning the first conductive layer. An interlayer insulation layer is deposited on the resultant structure, and a lower electrode and a dielectric layer having a high dielectric constant of a capacitor are formed to contact the source/drain region of the access transistor. By depositing a second conductive layer on the resultant structure having the dielectric layer and patterning the dielectric layer, a capacitor upper electrode is formed in the memory cell array area and a second resistor device is formed in the peripheral circuit area.

Abstract: A semiconductor memory device and a method of manufacturing same, wherein landing pads are formed to contact source/drain regions of an access transistor in a memory cell array area and a first resistor device is formed in the peripheral circuit area, by depositing a first conductive layer on a semiconductor substrate having an access transistor formed thereon and patterning the first conductive layer. An interlayer insulation layer is deposited on the resultant structure, and a lower electrode and a dielectric layer having a high dielectric constant of a capacitor are formed to contact the source/drain region of the access transistor. By depositing a second conductive layer on the resultant structure having the dielectric layer and patterning the dielectric layer, a capacitor upper electrode is formed in the memory cell array area and a second resistor device is formed in the peripheral circuit area.

Abstract: There is provided a method for fabricating a semiconductor device in which a plurality of adjacent contacts are formed on a plurality of regions having the same layout. The layout is divided into at least two groups, and the contacts are formed on the regions by using masks which are designed to have different sizes from each other by the group. By differentiating the mask sizing factor of the contact pattern by the group on the mask, it is possible to minimize the problem that the contact is not opened at the region where a global step difference on a wafer is significant and to enhance a process margin of photolithography.

Abstract: A semiconductor memory device and a method of manufacturing same, wherein landing pads are formed to contact source/drain regions of an access transistor in a memory cell array area and a first resistor device is formed in the peripheral circuit area, by depositing a first conductive layer on a semiconductor substrate having an access transistor formed thereon and patterning the first conductive layer. An interlayer insulation layer is deposited on the resultant structure, and a lower electrode and a dielectric layer having a high dielectric constant of a capacitor are formed to contact the source/drain region of the access transistor. By depositing a second conductive layer on the resultant structure having the dielectric layer and patterning the dielectric layer, a capacitor upper electrode is formed in the memory cell array area and a second resistor device is formed in the peripheral circuit area.

Abstract: There is provided a method for fabricating a semiconductor device in which a plurality of adjacent contacts are formed on a plurality of regions having the same layout. The layout is divided into at least two groups, and the contacts are formed on the regions by using masks which are designed to have different sizes from each other by the group. By differentiating the mask sizing factor of the contact pattern by the group on the mask, it is possible to minimize the problem that the contact is not opened at the region where a global step difference on a wafer is significant and to enhance a process margin of photolithography.