Patents by Inventor Kit-Lam Cheong
Kit-Lam Cheong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8051397Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.Type: GrantFiled: October 12, 2009Date of Patent: November 1, 2011Assignee: Cadence Design Systems, Inc.Inventors: Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Kit Lam Cheong, Patrick John Eichenseer
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Patent number: 7930675Abstract: Operations are performed in EDA tools that operate upon partitions or discrete portions of an electronic design, in which the partitions or discrete portions of the design are expanded to account for effects to/from other areas in the design. Identification is made of the portions of the design that are external to the partitions, and depending upon the type of expected effects, would then be considered during optimization and analysis of the partitions. This is implemented by logically expanding the partition to include consideration of the external portions during timing optimization and analysis. By considering an expanded partition for timing optimization and analysis, it is possible to identify unintended problems caused by the timing optimization at an earlier stage of the design process.Type: GrantFiled: December 26, 2007Date of Patent: April 19, 2011Assignee: Cadence Design Systems, Inc.Inventors: Oleg Levitsky, Kit Lam Cheong, Wilson Chan, Dongzi Liu
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Patent number: 7853905Abstract: The present invention relates to performing early design for testing (DFT)-aware prototyping of a design. Unlike prior approaches, the improvement analyzes and considers the impact of test structures at a very early stage of the design process. This allows test structures to be considered and addressed in a more efficient iterative and incremental way, which reduces design cycle time and reduces costs.Type: GrantFiled: December 27, 2007Date of Patent: December 14, 2010Assignee: Cadence Design Systems, Inc.Inventors: Kit Lam Cheong, Ping-Chih Wu, Weibin Ding, Louis Liu, Yiqun Ding
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Publication number: 20100122228Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.Type: ApplicationFiled: October 12, 2009Publication date: May 13, 2010Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Thaddeus Clay MCCRACKEN, Jong-Chang LEE, Ping-Chih WU, Cecile NGHIEM, Kit Lam CHEONG, Patrick John EICHENSEER
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Patent number: 7603643Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.Type: GrantFiled: January 30, 2007Date of Patent: October 13, 2009Assignee: Cadence Design Systems, Inc.Inventors: Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Kit Lam Cheong, Patrick John Eichenseer
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Publication number: 20090172619Abstract: Operations are performed in EDA tools that operate upon partitions or discrete portions of an electronic design, in which the partitions or discrete portions of the design are expanded to account for effects to/from other areas in the design. Identification is made of the portions of the design that are external to the partitions, and depending upon the type of expected effects, would then be considered during optimization and analysis of the partitions. This is implemented by logically expanding the partition to include consideration of the external portions during timing optimization and analysis. By considering an expanded partition for timing optimization and analysis, it is possible to identify unintended problems caused by the timing optimization at an earlier stage of the design process.Type: ApplicationFiled: December 26, 2007Publication date: July 2, 2009Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Oleg Levitsky, Kit Lam Cheong, Wilson Chan, Dongzi Liu
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Publication number: 20080184184Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.Type: ApplicationFiled: January 30, 2007Publication date: July 31, 2008Applicant: Cadence Design Systems, Inc.Inventors: Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Kit Lam Cheong, Patrick John Eichenseer
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Patent number: 6651235Abstract: An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition.Type: GrantFiled: October 30, 2001Date of Patent: November 18, 2003Assignee: Cadence Design Systems, Inc.Inventors: Wei-Jin Dai, Kit-Lam Cheong, Hsi-Chuan Chen, Wei-Lun Kao
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Patent number: 6578183Abstract: When generating a layout for an integrated; circuit (IC) based on a netlist design, a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced. The trial layout acts as a basis for estimating sizes and positions of substrate areas needed to accommodate various modules of the IC and for estimating delays through various signal paths having timing constraints. After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout. A floor plan is created which imposes spatial constraints on each partition based on the estimated size and position within the trial layout of the modules forming the partition. A timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout.Type: GrantFiled: October 22, 2001Date of Patent: June 10, 2003Assignee: Silicon Perspective CorporationInventors: Kit-Lam Cheong, Wei-Jin Dai, Hsi-Chuan Chen, Patrick John Eichenseer
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Publication number: 20030084416Abstract: An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition.Type: ApplicationFiled: October 30, 2001Publication date: May 1, 2003Inventors: Wei-Jin Dai, Kit-Lam Cheong, Hsi-Chuan Chen, Wei-Lun Kao
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Publication number: 20030079192Abstract: When generating a layout for an integrated circuit (IC) based on a netlist design, a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced. The trial layout acts as a basis for estimating sizes and positions of substrate areas needed to accommodate various modules of the IC and for estimating delays through various signal paths having timing constraints. After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout. A floor plan is created which imposes spatial constraints on each partition based on the estimated size and position within the trial layout of the modules forming the partition. A timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout.Type: ApplicationFiled: October 22, 2001Publication date: April 24, 2003Inventors: Kit-Lam Cheong, Wei-Jin Dai, Hsi-Chuan Chen, Patrick John Eichenseer