Patents by Inventor Kit S. Tam
Kit S. Tam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11410032Abstract: A computer system for performing negative sampling, including a processor chip having a plurality of on-chip memory banks, a plurality of on-chip compute engines and a memory interface, wherein the on-chip memory banks include memory blocks that store corresponding sets of ‘likely to be updated’ word vectors, a memory block that stores a subset of ‘less likely to be updated’ word vectors and a noise sample cache that stores a subset of negative samples. An external memory is coupled to the memory interface, and stores a set of ‘less likely to be updated’ word vectors and a set of negative samples. The on-chip compute engines include a refresh thread, which accesses the set of negative samples in the external memory to provide the subset of negative samples stored in the noise sample cache on the processor chip, such that these negative samples can be readily accessed on the processor chip.Type: GrantFiled: June 21, 2019Date of Patent: August 9, 2022Assignee: DeGirum CorporationInventors: Kit S. Tam, Shashi Kiran Chilappagari
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Patent number: 11197114Abstract: An extended cognitive loudspeaker system (CLS) including a system manager coupled to a basic service set (BSS) of a wireless network, wherein the system manager establishes a CLS network using an independent BSS (IBSS) of the wireless network. A first CLS playgroup is formed by the system manager through the CLS network IBSS, wherein the first CLS playgroup includes a first control station (CS) and a first group of sound production stations (SPSs). A second CLS playgroup is formed by the system manager through the CLS network IBBS, wherein the second CLS playgroup includes a second CS station and a second group of SPSs. The second CLS playgroup can be dissolved, and the first CLS playgroup can be modified to include the second group of SPSs. The second group of SPSs can include mobility functions to enable any required movement of the second group of SPSs.Type: GrantFiled: November 23, 2020Date of Patent: December 7, 2021Inventor: Kit S. Tam
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Patent number: 11196587Abstract: A permutated ring network includes a plurality of bi-directional source-synchronous ring networks, each having a plurality of data transport stations, and a plurality of communication nodes. Each of the communication nodes is coupled to one of the data transport stations in each of the plurality of bi-directional source-synchronous ring networks.Type: GrantFiled: November 17, 2017Date of Patent: December 7, 2021Assignee: DeGirum CorporationInventors: Kit S. Tam, Winston Lee
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Patent number: 11140480Abstract: A system includes a CS playback device that establishes a secure communication channel with a media source device on a wireless medium, wherein the CS playback device receives and decodes a media stream transmitted from the media source device on the secure communication channel, thereby providing a decoded media stream. The CS playback device generates playback clock messages based on the decoded media stream, and transmits these playback clock messages on a wireless communication channel. One or more SPS playback devices are provided, each storing information enabling the SPS playback device to receive and decode the media stream transmitted from the media source device on the secure communication channel, whereby each SPS playback device extracts audio playback messages from the media stream.Type: GrantFiled: September 22, 2020Date of Patent: October 5, 2021Inventor: Kit S. Tam
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Patent number: 11108486Abstract: A cognitive loudspeaker system includes a control station (CS) that broadcasts clock control messages and separate playback messages to a plurality of sound production stations (SPSs). The clock control messages are generated in response to a CS clock signal. Each SPS generates a corresponding local conductor clock signal in response to the received control clock messages and a local SPS clock signal, such that all of the local conductor clock signals are synchronized. Each SPS also generates local digital playback samples in response to the received playback messages. The local digital playback samples are written to an output buffer in response to the local SPS clock signal, and are read from the output buffer in response to the local conductor clock signal.Type: GrantFiled: September 6, 2019Date of Patent: August 31, 2021Inventor: Kit S. Tam
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Publication number: 20210160639Abstract: An extended cognitive loudspeaker system (CLS) including a system manager coupled to a basic service set (BSS) of a wireless network, wherein the system manager establishes a CLS network using an independent BSS (IBSS) of the wireless network. A first CLS playgroup is formed by the system manager through the CLS network IBSS, wherein the first CLS playgroup includes a first control station (CS) and a first group of sound production stations (SPSs). A second CLS playgroup is formed by the system manager through the CLS network IBBS, wherein the second CLS playgroup includes a second CS station and a second group of SPSs. The second CLS playgroup can be dissolved, and the first CLS playgroup can be modified to include the second group of SPSs. The second group of SPSs can include mobility functions to enable any required movement of the second group of SPSs.Type: ApplicationFiled: November 23, 2020Publication date: May 27, 2021Inventor: Kit S. Tam
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Publication number: 20210092520Abstract: A system includes a CS playback device that establishes a secure communication channel with a media source device on a wireless medium, wherein the CS playback device receives and decodes a media stream transmitted from the media source device on the secure communication channel, thereby providing a decoded media stream. The CS playback device generates playback clock messages based on the decoded media stream, and transmits these playback clock messages on a wireless communication channel. One or more SPS playback devices are provided, each storing information enabling the SPS playback device to receive and decode the media stream transmitted from the media source device on the secure communication channel, whereby each SPS playback device extracts audio playback messages from the media stream.Type: ApplicationFiled: September 22, 2020Publication date: March 25, 2021Inventor: Kit S. Tam
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Publication number: 20210075533Abstract: A cognitive loudspeaker system includes a control station (CS) that broadcasts clock control messages and separate playback messages to a plurality of sound production stations (SPSs). The clock control messages are generated in response to a CS clock signal. Each SPS generates a corresponding local conductor clock signal in response to the received control clock messages and a local SPS clock signal, such that all of the local conductor clock signals are synchronized. Each SPS also generates local digital playback samples in response to the received playback messages. The local digital playback samples are written to an output buffer in response to the local SPS clock signal, and are read from the output buffer in response to the local conductor clock signal.Type: ApplicationFiled: September 6, 2019Publication date: March 11, 2021Inventor: Kit S. Tam
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Patent number: 10691632Abstract: A computer architecture that connects a plurality of compute engines and memory banks using one or more permutated ring networks to provide a scalable, high-bandwidth, low-latency point-to-point multi-chip communications solution.Type: GrantFiled: March 14, 2019Date of Patent: June 23, 2020Assignee: DeGIRUM CorporationInventor: Kit S. Tam
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Publication number: 20190392315Abstract: A computer system for performing negative sampling, including a processor chip having a plurality of on-chip memory banks, a plurality of on-chip compute engines and a memory interface, wherein the on-chip memory banks include memory blocks that store corresponding sets of ‘likely to be updated’ word vectors, a memory block that stores a subset of ‘less likely to be updated’ word vectors and a noise sample cache that stores a subset of negative samples. An external memory is coupled to the memory interface, and stores a set of ‘less likely to be updated’ word vectors and a set of negative samples. The on-chip compute engines include a refresh thread, which accesses the set of negative samples in the external memory to provide the subset of negative samples stored in the noise sample cache on the processor chip, such that these negative samples can be readily accessed on the processor chip.Type: ApplicationFiled: June 21, 2019Publication date: December 26, 2019Inventors: Kit S. Tam, Shashi Kiran Chilappagari
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Patent number: 10476656Abstract: A plurality of synchronization FIFOs receive input data streams from corresponding transmitting agents. Data is written to the synchronization FIFOs based on write clock signals provided by the corresponding transmitting agents. An arbitration circuit reads data from the synchronization FIFOs based on an asynchronous local clock signal. A minimum number of entries (SMIN) of each synchronization FIFO is specified by a number of entries required to synchronize the stored data to the local clock signal. SMIN may further be specified by: a number of entries required to store data during a threshold time period that a throughput of the input data streams may exceed a read data throughput enabled by the local clock signal; a number of entries required to store the data during a flow control response time; and a number of entries read from the synchronization FIFO during the threshold time period and the flow control response time.Type: GrantFiled: April 13, 2018Date of Patent: November 12, 2019Assignee: DeGirum CorporationInventors: Winston Lee, Kit S. Tam
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Publication number: 20190319775Abstract: A plurality of synchronization FIFOs receive input data streams from corresponding transmitting agents. Data is written to the synchronization FIFOs based on write clock signals provided by the corresponding transmitting agents. An arbitration circuit reads data from the synchronization FIFOs based on an asynchronous local clock signal. A minimum number of entries (SMIN) of each synchronization FIFO is specified by a number of entries required to synchronize the stored data to the local clock signal. SMIN may further be specified by: a number of entries required to store data during a threshold time period that a throughput of the input data streams may exceed a read data throughput enabled by the local clock signal; a number of entries required to store the data during a flow control response time; and a number of entries read from the synchronization FIFO during the threshold time period and the flow control response time.Type: ApplicationFiled: April 13, 2018Publication date: October 17, 2019Inventors: Winston Lee, Kit S. Tam
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Patent number: 10411910Abstract: A ring network architecture includes multiple communication nodes configured in a ring. Wave pipelining is used to provide for high bandwidth and low latency on-chip communications. Each node implements a source-synchronized clocking scheme, such that there is no need to build an extensive low skew clock-tree across a large die area. A single reference clock signal is generated within a root node, and is routed through each of the nodes of the ring network in a unidirectional manner. Each node includes a timestamp counter and a color bit register, which store values that enable the node to resolve ordered transaction messages issued by the other nodes in a precise order, even though the nodes are operating independently, and receive the various transaction messages in totally different timing orders. Because the control logic is distributed among the nodes, no centralized controller is necessary.Type: GrantFiled: November 17, 2017Date of Patent: September 10, 2019Assignee: DeGirum CorporationInventor: Kit S. Tam
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Publication number: 20180145849Abstract: A ring network architecture includes multiple communication nodes configured in a ring. Wave pipelining is used to provide for high bandwidth and low latency on-chip communications. Each node implements a source-synchronized clocking scheme, such that there is no need to build an extensive low skew clock-tree across a large die area. A single reference clock signal is generated within a root node, and is routed through each of the nodes of the ring network in a unidirectional manner. Each node includes a timestamp counter and a color bit register, which store values that enable the node to resolve ordered transaction messages issued by the other nodes in a precise order, even though the nodes are operating independently, and receive the various transaction messages in totally different timing orders. Because the control logic is distributed among the nodes, no centralized controller is necessary.Type: ApplicationFiled: November 17, 2017Publication date: May 24, 2018Inventor: Kit S. Tam
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Publication number: 20180145850Abstract: A permutated ring network includes a plurality of bi-directional source-synchronous ring networks, each having a plurality of data transport stations, and a plurality of communication nodes. Each of the communication nodes is coupled to one of the data transport stations in each of the plurality of bi-directional source-synchronous ring networks.Type: ApplicationFiled: November 17, 2017Publication date: May 24, 2018Inventors: Kit S. Tam, Winston Lee
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Patent number: 9282418Abstract: A cognitive loudspeaker system including a control station that communicates wirelessly and bi-directionally with a plurality of sound production stations. The control station and the sound production stations are initially synchronized to a conductor clock. Configuration information is then transmitted from the sound production stations to the control station. In response, the control station generates playback executables, which are transmitted to the sound production stations. The control station also transmits digital audio information to the sound production stations. Within each sound production station, the previously received playback executable is used to control the decoding and processing of the received digital audio information. Each sound production station generates digital audio output samples, which are converted to analog output signals. These analog output signals are amplified and are used to drive loudspeakers.Type: GrantFiled: April 29, 2011Date of Patent: March 8, 2016Inventor: Kit S. Tam
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Publication number: 20110270428Abstract: A cognitive loudspeaker system including a control station that communicates wirelessly and bi-directionally with a plurality of sound production stations. The control station and the sound production stations are initially synchronized to a conductor clock. Configuration information is then transmitted from the sound production stations to the control station. In response, the control station generates playback executables, which are transmitted to the sound production stations. The control station also transmits digital audio information to the sound production stations. Within each sound production station, the previously received playback executable is used to control the decoding and processing of the received digital audio information. Each sound production station generates digital audio output samples, which are converted to analog output signals. These analog output signals are amplified and are used to drive loudspeakers.Type: ApplicationFiled: April 29, 2011Publication date: November 3, 2011Inventor: Kit S. Tam