Abstract: Write check bits are generated in a predictive manner for partial-word write transactions in a memory system implementing error code correction. A read data word and associated read check bits are read from an address of the memory. If an error exists in a byte of the read data word, this byte is identified. At the same time, one or more bytes of the uncorrected read data word are merged with one or more bytes of a write data word, thereby creating a merged data word. Write check bits are generated in response to the merged data word. If the merged data word includes a byte of the read data word, which contains an error, the write check bits are modified to reflect this error. The merged data word and the modified (or unmodified) write check bits are then written to the address of the memory.

Abstract: A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory interface and an error detection/correction unit. The memory array is configured to store test data patterns and corresponding error correction code (ECC) values. The memory interface is configured such that the ECC values are not directly accessible. The error detection/correction unit is configured to correct single-bit errors in the test data patterns and corresponding ECC values. A set of test data patterns associated with the semiconductor memory is selected such that any multiple-bit error in a test data pattern and the corresponding ECC value causes the error detection/correction unit to provide an output data pattern having an error, thereby rendering multiple-bit faults 100% detectable.

Abstract: A technique for eliminating the performance penalty of implementing jump instructions in a deeply pipelined processor includes a pipeline having a signal for indicating that the top of the address return stack has been updated by an address moved to the return register. An instruction moving a previously computed jump target address to the return register is included in code to be executed. The pipeline uses the instruction at the top of the RAS as a guess of the target instruction of a fetched jump instruction and immediately begins fetching instructions indicated by the guess.