Abstract: An inter-die double data rate (DDR) data transfer scheme is provided. In particular, the data transfer scheme utilizes an error correction code (ECC) encoding scheme that exploits the DDR property that a single microbump defect can only yield four possible error scenarios. A specialized single error correcting, double error detecting, and double adjacent error correcting (SEC-DED-DAEC) encoding scheme that imposes at least four parity check matrix constraints may be used. Configured and operated in this way, a fewer number of parity check bits are required to detect data bit errors associated with a single defective microbump.

Abstract: An inter-die double data rate (DDR) data transfer scheme is provided. In particular, the data transfer scheme utilizes an error correction code (ECC) encoding scheme that exploits the DDR property that a single microbump defect can only yield four possible error scenarios. A specialized single error correcting, double error detecting, and double adjacent error correcting (SEC-DED-DAEC) encoding scheme that imposes at least four parity check matrix constraints may be used. Configured and operated in this way, a fewer number of parity check bits are required to detect data bit errors associated with a single defective microbump.

Abstract: A method includes detecting an open in a first IO element of a first bank of IOs and not in a second bank of IOs. The first and second banks of IOs are in a channel of a first die. The method includes shifting a first connection between the first IO element and a first core fabric of the first die to second connection between a second IO element and the first core fabric. The second IO element is in the first bank of IOs. The method includes shifting a third connection between a third IO element and a second core fabric of a second die to fourth connection between a fourth IO element and the second core fabric. The third and fourth IO elements are in a third bank of IOs of the second die. The method includes not shifting connections in the second and fourth banks of IOs.

Abstract: An inter-die double data rate (DDR) data transfer scheme is provided. In particular, the data transfer scheme utilizes an error correction code (ECC) encoding scheme that exploits the DDR property that a single microbump defect can only yield four possible error scenarios. A specialized single error correcting, double error detecting, and double adjacent error correcting (SEC-DED-DAEC) encoding scheme that imposes at least four parity check matrix constraints may be used. Configured and operated in this way, a fewer number of parity check bits are required to detect data bit errors associated with a single defective microbump.

Abstract: A prioritized error detection schedule may be generated using computer-aided-design (CAD) tools that receive specifications of critical regions within an array of configuration random access memory (CRAM) cells on an integrated circuit. Each of the specified critical regions may be provided a respective criticality weight. The proportion of indices in a prioritized error detection schedule that prescribe error detection for a given critical region may be based on the criticality weight of the given critical region. A prioritized error detection schedule may prescribe more frequent error correction for critical regions with higher criticality weights relative to critical regions with lower criticality weights. Addressing circuitry on the integrated circuit may be used to read out data from critical regions of CRAM in the order prescribed by the prioritized error detection schedule and check the read out CRAM data for errors.

Abstract: A method includes detecting an open in a first IO element of a first bank of IOs and not in a second bank of IOs. The first and second banks of IOs are in a channel of a first die. The method includes shifting a first connection between the first IO element and a first core fabric of the first die to second connection between a second IO element and the first core fabric. The second IO element is in the first bank of IOs. The method includes shifting a third connection between a third IO element and a second core fabric of a second die to fourth connection between a fourth IO element and the second core fabric. The third and fourth IO elements are in a third bank of IOs of the second die. The method includes not shifting connections in the second and fourth banks of IOs.

Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

Abstract: A prioritized error detection schedule may be generated using computer-aided-design (CAD) tools that receive specifications of critical regions within an array of configuration random access memory (CRAM) cells on an integrated circuit. Each of the specified critical regions may be provided a respective criticality weight. The proportion of indices in a prioritized error detection schedule that prescribe error detection for a given critical region may be based on the criticality weight of the given critical region. A prioritized error detection schedule may prescribe more frequent error correction for critical regions with higher criticality weights relative to critical regions with lower criticality weights. Addressing circuitry on the integrated circuit may be used to read out data from critical regions of CRAM in the order prescribed by the prioritized error detection schedule and check the read out CRAM data for errors.

Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

Abstract: A method of operating an integrated circuit that includes a plurality of registers may include receiving a sleep mode request for the integrated circuit. The sleep mode request may be a control signal received with control circuitry on the integrated circuit. The plurality of registers may be configured to operate as a scan chain when the sleep mode request is received. Integrated circuit state information that are stored in the plurality of registers may be retrieved by operating the scan chain and stored in a memory module. The integrated circuit may be placed in a sleep mode. Placing the integrated circuit in the sleep mode may reduce power consumption of the integrated circuit.

Abstract: Techniques and mechanisms dynamically configure shift registers among registers composing data registers in a circuit such as a Programmable Logic Device (PLD). A configuration bit stream used to configure the PLD may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. Shift registers may be dynamically configured such that registers which do not correspond to physical configuration elements may be skipped. Thus, a PLD may be programmed with a configuration bit stream without phantom bits.

Abstract: Techniques and mechanisms dynamically configure shift registers among registers composing data registers in a circuit such as a Programmable Logic Device (PLD). A configuration bit stream used to configure the PLD may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. Shift registers may be dynamically configured such that registers which do not correspond to physical configuration elements may be skipped. Thus, a PLD may be programmed with a configuration bit stream without phantom bits.

Abstract: An integrated circuit (IC) includes a circuit, an encoder, and a decoder. The circuit is coupled to circuitry in the IC via a first set of interconnect fabricated using a metal layer. The encoder encodes a plurality of address lines to provide a plurality of encoded address lines. The decoder decodes the plurality of address lines. The plurality of encoded address lines are routed using a second set of interconnect fabricated using the metal layer.

Abstract: Integrated circuits with error detection circuitry are provided. Integrated circuits may include memory cells organized into frames. The error detection circuitry may compress each frame to scan for soft errors. The error detection circuitry may include multiple input shift registers (MISRs), a data register, and a signature comparator. The data frames may be read, compressed, and shifted into the MISRs in parallel. After all the data frames have been read, the MISRs may provide a scanned MISR signature at their outputs. Computer-aided design (CAD) tools may be used to calculate a precomputed MISR signature. The precomputed MISR signature may be loaded into the data register. The signature comparator compares the scanned MISR signature with the precomputed MISR signature. If the signatures match, then the device is free of soft errors. If the signatures do not match, then at least one soft error exists.

Abstract: Methods and circuits for zeroization verification of the memory in an integrated circuit (IC) are provided. One method includes sequentially reading frames from a block of the memory, and sequentially performing a logical operation between each of the frames and the content of a signature register. The result of the logical operation is stored back in the signature register. In another operation, a hardware logical comparison is made between a device hardwired signature block and the content of the signature register, after the logical operations for all the frames have been performed. The device hardwired signature block is a hardware implemented constant that is unavailable for loading in registers of the IC. The block of the memory is verified to hold a fixed value when the result of the hardware logical comparison indicates that the device hardwired signature block is equal to the content of the signature register.