Patents by Inventor Ki-Vin Im

Ki-Vin Im has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250081482
    Abstract: Embodiments of the present invention provide a semiconductor device capable of improving current leakage property and a method for fabricating the same. According to an embodiment of the present invention, a capacitor comprises: a lower electrode; a dielectric layer over the lower electrode; and an upper electrode over the dielectric layer, the upper electrode including a conductive carbon-containing layer, wherein a carbon content in the conductive carbon-containing layer is more than 5 at % and equal to or less than 10 at %.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 6, 2025
    Inventors: Kwan Woo DO, Wan Joo MAENG, Jeong Yeop LEE, Ki Vin IM
  • Patent number: 12218182
    Abstract: Embodiments of the present invention provide a semiconductor device capable of improving current leakage property and a method for fabricating the same. According to an embodiment of the present invention, a capacitor comprises: a lower electrode; a dielectric layer over the lower electrode; and an upper electrode over the dielectric layer, the upper electrode including a conductive carbon-containing layer, wherein a carbon content in the conductive carbon-containing layer is more than 5 at % and equal to or less than 10 at %.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: February 4, 2025
    Assignee: SK hynix Inc.
    Inventors: Kwan Woo Do, Wan Joo Maeng, Jeong Yeop Lee, Ki Vin Im
  • Publication number: 20250022655
    Abstract: A semiconductor device includes: a first electrode; a booster layer over the first electrode; a hafnium-zirconium based layer over the booster layer; and a second electrode over the hafnium-zirconium based layer.
    Type: Application
    Filed: September 30, 2024
    Publication date: January 16, 2025
    Inventors: Se-Hun KANG, Han-Joon KIM, Ki-Vin IM
  • Patent number: 12199140
    Abstract: A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.
    Type: Grant
    Filed: March 25, 2024
    Date of Patent: January 14, 2025
    Assignee: SK hynix Inc.
    Inventors: Jae Hee Song, Dong Hyun Lee, Kyung Woong Park, Cheol Hwan Park, Ki Vin Im
  • Patent number: 12106904
    Abstract: A semiconductor device includes: a first electrode; a second electrode; and a multi-layered stack including a hafnium oxide layer of a tetragonal crystal structure which is positioned between the first electrode and the second electrode, wherein the multi-layered stack includes: a seed layer for promoting tetragonal crystallization of the hafnium oxide layer and having a tetragonal crystal structure; and a booster layer for boosting a dielectric constant of the hafnium oxide layer.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: October 1, 2024
    Assignee: SK hynix Inc.
    Inventors: Se-Hun Kang, Han-Joon Kim, Ki-Vin Im
  • Publication number: 20240234489
    Abstract: A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.
    Type: Application
    Filed: March 25, 2024
    Publication date: July 11, 2024
    Inventors: Jae Hee SONG, Dong Hyun LEE, Kyung Woong PARK, Cheol Hwan PARK, Ki Vin IM
  • Patent number: 11973106
    Abstract: A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: April 30, 2024
    Assignee: SK hynix Inc.
    Inventors: Jae Hee Song, Dong Hyun Lee, Kyung Woong Park, Cheol Hwan Park, Ki Vin Im
  • Publication number: 20230215910
    Abstract: A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.
    Type: Application
    Filed: July 5, 2022
    Publication date: July 6, 2023
    Inventors: Jae Hee SONG, Dong Hyun LEE, Kyung Woong PARK, Cheol Hwan PARK, Ki Vin IM
  • Publication number: 20220416055
    Abstract: A semiconductor device includes: a first electrode; a second electrode; and a dielectric layer stack positioned between the first electrode and the second electrode, the dielectric layer stack including a first anti-ferroelectric layer, a second anti-ferroelectric layer, and a ferroelectric layer between the first anti-ferroelectric layer and the second anti-ferroelectric.
    Type: Application
    Filed: August 30, 2022
    Publication date: December 29, 2022
    Inventors: Wan Joo MAENG, Hyun Soo JIN, Se Hun KANG, Ki Vin IM, Kyoung Ryul YOON
  • Publication number: 20220399435
    Abstract: The present invention relates to a semiconductor device having a capacitor and a method for fabricating the same. A semiconductor device may comprise: a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed over the lower electrode and the supporter; an upper electrode formed on the dielectric layer; and a dielectric booster layer disposed between the lower electrode and the dielectric layer, and selectively formed on a surface of the lower electrode.
    Type: Application
    Filed: February 4, 2022
    Publication date: December 15, 2022
    Inventors: Lynn LEE, Wan Joo MAENG, Jae Hee SONG, Ki Vin IM
  • Publication number: 20220359643
    Abstract: Embodiments of the present invention provide a semiconductor device capable of improving current leakage property and a method for fabricating the same. According to an embodiment of the present invention, a capacitor comprises: a lower electrode; a dielectric layer over the lower electrode; and an upper electrode over the dielectric layer, the upper electrode including a conductive carbon-containing layer, wherein a carbon content in the conductive carbon-containing layer is more than 5 at % and equal to or less than 10 at %.
    Type: Application
    Filed: November 2, 2021
    Publication date: November 10, 2022
    Inventors: Kwan Woo DO, Wan Joo MAENG, Jeong Yeop LEE, Ki Vin IM
  • Publication number: 20220351903
    Abstract: A semiconductor device includes: a first electrode; a second electrode; and a multi-layered stack including a hafnium oxide layer of a tetragonal crystal structure which is positioned between the first electrode and the second electrode, wherein the multi-layered stack includes: a seed layer for promoting tetragonal crystallization of the hafnium oxide layer and having a tetragonal crystal structure; and a booster layer for boosting a dielectric constant of the hafnium oxide layer.
    Type: Application
    Filed: July 8, 2022
    Publication date: November 3, 2022
    Inventors: Se-Hun KANG, Han-Joon KIM, Ki-Vin IM
  • Patent number: 11469310
    Abstract: A semiconductor device includes: a first electrode; a second electrode; and a dielectric layer stack positioned between the first electrode and the second electrode, the dielectric layer stack including a first anti-ferroelectric layer, a second anti-ferroelectric layer, and a ferroelectric layer between the first anti-ferroelectric layer and the second anti-ferroelectric.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: October 11, 2022
    Assignee: SK hynix Inc.
    Inventors: Wan Joo Maeng, Hyun Soo Jin, Se Hun Kang, Ki Vin Im, Kyoung Ryul Yoon
  • Patent number: 11410813
    Abstract: A semiconductor device includes: a first electrode; a second electrode; and a multi-layered stack including a hafnium oxide layer of a tetragonal crystal structure which is positioned between the first electrode and the second electrode, wherein the multi-layered stack includes: a seed layer for promoting tetragonal crystallization of the hafnium oxide layer and having a tetragonal crystal structure; and a booster layer for boosting a dielectric constant of the hafnium oxide layer.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: August 9, 2022
    Assignee: SK hynix Inc.
    Inventors: Se-Hun Kang, Han-Joon Kim, Ki-Vin Im
  • Publication number: 20210359100
    Abstract: A semiconductor device includes: a first electrode; a second electrode; and a dielectric layer stack positioned between the first electrode and the second electrode, the dielectric layer stack including a first anti-ferroelectric layer, a second anti-ferroelectric layer, and a ferroelectric layer between the first anti-ferroelectric layer and the second anti-ferroelectric.
    Type: Application
    Filed: November 12, 2020
    Publication date: November 18, 2021
    Inventors: Wan Joo MAENG, Hyun Soo JIN, Se Hun KANG, Ki Vin IM, Kyoung Ryul YOON
  • Publication number: 20210142946
    Abstract: A semiconductor device includes: a first electrode; a second electrode; and a multi-layered stack including a hafnium oxide layer of a tetragonal crystal structure which is positioned between the first electrode and the second electrode, wherein the multi-layered stack includes: a seed layer for promoting tetragonal crystallization of the hafnium oxide layer and having a tetragonal crystal structure; and a booster layer for boosting a dielectric constant of the hafnium oxide layer.
    Type: Application
    Filed: May 4, 2020
    Publication date: May 13, 2021
    Inventors: Se-Hun KANG, Han-Joon KIM, Ki-Vin IM
  • Patent number: 9716094
    Abstract: A semiconductor device having a capacitor includes a substrate which has a transistor, a first insulating pattern which is formed on the substrate and does not overlap a first contact node formed in the substrate, a second insulating pattern which is formed on the substrate, does not overlap a second contact node formed in the substrate, and is separated from the first insulating pattern, a first lower electrode which is formed on part of the substrate and sidewalls of the first insulating pattern, a second lower electrode which is formed on part of the substrate and sidewalls of the second insulating pattern, a dielectric layer pattern which is formed on the first lower electrode and the second lower electrode, and an upper electrode which is formed on the dielectric layer pattern. Related fabrication methods are also discussed.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: July 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yeol Kang, Ki-Vin Im, Youn-Soo Kim, Han-Jin Lim
  • Patent number: 9646971
    Abstract: Semiconductor devices and fabricating methods thereof are provided. A semiconductor device may include a substrate, a metal layer on the substrate, a seed layer on the metal layer, a nanowire including a pillar shape on the seed layer, a dielectric film conformally covering the nanowire, and an electrode film on the dielectric film.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 9, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hyun Im, Han-Jin Lim, Jin-Won Ma, Kong-Soo Lee, Ki-Vin Im
  • Publication number: 20170098652
    Abstract: A semiconductor device having a capacitor includes a substrate which has a transistor, a first insulating pattern which is formed on the substrate and does not overlap a first contact node formed in the substrate, a second insulating pattern which is formed on the substrate, does not overlap a second contact node formed in the substrate, and is separated from the first insulating pattern, a first lower electrode which is formed on part of the substrate and sidewalls of the first insulating pattern, a second lower electrode which is formed on part of the substrate and sidewalls of the second insulating pattern, a dielectric layer pattern which is formed on the first lower electrode and the second lower electrode, and an upper electrode which is formed on the dielectric layer pattern. Related fabrication methods are also discussed.
    Type: Application
    Filed: August 5, 2016
    Publication date: April 6, 2017
    Inventors: Sang-Yeol Kang, Ki-Vin Im, Youn-Soo Kim, Han-Jin Lim
  • Publication number: 20170062435
    Abstract: Semiconductor devices and fabricating methods thereof are provided. A semiconductor device may include a substrate, a metal layer on the substrate, a seed layer on the metal layer, a nanowire including a pillar shape on the seed layer, a dielectric film conformally covering the nanowire, and an electrode film on the dielectric film.
    Type: Application
    Filed: May 24, 2016
    Publication date: March 2, 2017
    Inventors: Dong-Hyun IM, Han-Jin LIM, Jin-Won MA, Kong-Soo LEE, Ki-Vin IM