Abstract: An electronic system includes a first interposer including first signal paths, a second interposer spaced apart from the first interposer and including second signal paths, a first semiconductor chip structure on the first and second interposers and including a first circuit region and a second circuit region, and a second semiconductor chip structure on the first and second interposers and spaced apart from the first semiconductor chip structure. The second semiconductor chip structure includes a third circuit region configured to communicate with the first circuit region of the first semiconductor chip structure at a first rate through the first signal paths of the first interposer and a fourth circuit region configured to communicate with the second circuit region of the first semiconductor chip structure at a second rate, different from the first rate, through the second signal paths of the second interposer.

Abstract: An electronic system includes a first interposer including first signal paths, a second interposer spaced apart from the first interposer and including second signal paths, a first semiconductor chip structure on the first and second interposers and including a first circuit region and a second circuit region, and a second semiconductor chip structure on the first and second interposers and spaced apart from the first semiconductor chip structure. The second semiconductor chip structure includes a third circuit region configured to communicate with the first circuit region of the first semiconductor chip structure at a first rate through the first signal paths of the first interposer and a fourth circuit region configured to communicate with the second circuit region of the first semiconductor chip structure at a second rate, different from the first rate, through the second signal paths of the second interposer.

Abstract: Provided is a semiconductor package including a package substrate including a substrate pad, a first chip stacked structure including a first base chip mounted on an upper surface of the package substrate, and one or more first stacked chips sequentially offset-stacked along a first direction on the first base chip, a second chip stacked structure including a second base chip offset-stacked along the first direction on an upper surface of the first chip stacked structure, and one or more second stacked chips sequentially offset-stacked along the first direction on the second base chip, a bonding wire, and a first support mounted on the package substrate to be spaced apart from the first chip stacked structure in the first direction and supporting the second chip stacked structure, wherein the first support supports the second chip stacked structure by supporting a lower surface of the second base chip.

Abstract: A semiconductor package includes a substrate including first bonding pads. At least one chip stack is on the substrate and includes a plurality of semiconductor chips stacked thereon. The semiconductor chips include first connection pads electrically connected to the first bonding pads, bonding wires electrically connecting the substrate to the chip stack, and connection bumps below the substrate. The semiconductor chips include a second group of semiconductor chips stacked on a first group of semiconductor chips. An uppermost semiconductor chip in the first group of semiconductor chips or a lowermost semiconductor chip in the second group of semiconductor chips further includes second connection pads electrically connected to the first connection pads, respectively.

Abstract: Provided is a semiconductor package having improved signal integrity (SI) and a chip stack structure of a plurality of semiconductor chips. The semiconductor package includes a package substrate, a chip stack structure on the package substrate and including at least two semiconductor chips, and an external connection terminal on a lower surface of the package substrate. A first semiconductor chip arranged uppermost in the chip stack structure is connected to a first bonding pad of the package substrate through a first wire. A second semiconductor chip arranged under the first semiconductor chip in the chip stack structure is connected to a second bonding pad of the package substrate through a second wire. When the first bonding pad is farther from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate.

Abstract: Provided is a semiconductor package having improved signal integrity (SI) and a chip stack structure of a plurality of semiconductor chips. The semiconductor package includes a package substrate, a chip stack structure on the package substrate and including at least two semiconductor chips, and an external connection terminal on a lower surface of the package substrate. A first semiconductor chip arranged uppermost in the chip stack structure is connected to a first bonding pad of the package substrate through a first wire. A second semiconductor chip arranged under the first semiconductor chip in the chip stack structure is connected to a second bonding pad of the package substrate through a second wire. When the first bonding pad is farther from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate.

Abstract: A substrate is provided. The substrate includes a body layer that includes a signal area; a first wiring layer provided on a lower surface of the body layer, the first wiring layer including a plurality of first signal lines provided in the signal area and a first power line provided outside the signal area; and a second wiring layer provided on an upper surface of the body layer, the second wiring layer including a plurality of second signal lines provided in the signal area and a second power line provided outside the signal area.

Abstract: A semiconductor device and semiconductor package, the device including a lower semiconductor chip including a lower through-electrode; an interposer mounted on the lower semiconductor chip, the interposer including an interposer substrate; a plurality of interposer through-electrodes penetrating through at least a portion of the interposer substrate in a vertical direction and electrically connected to the lower through-electrode; and at least one capacitor in the interposer substrate and electrically connected to at least one interposer through-electrode of the plurality of interposer through-electrodes; and an upper semiconductor chip mounted on the interposer and electrically connected to the interposer through-electrode.

Abstract: Provided is a semiconductor package including a first substrate, a first pattern and a second pattern disposed on the first substrate, a semiconductor chip disposed on the first substrate and including a metal layer, a circuit structure disposed on the metal layer of the semiconductor chip, and a plurality of first bumps disposed between the first substrate and the semiconductor chip and electrically connected to the first pattern, wherein the first pattern includes a ground pattern or a power pattern, the first substrate includes a first region overlapping the circuit structure in a vertical direction, the plurality of first bumps are disposed adjacent to the first region on a top surface of the first substrate, and a first bump of the plurality of first bumps has an elongated shape substantially parallel to an adjacent side of the first region.

Abstract: A semiconductor device and semiconductor package, the device including a lower semiconductor chip including a lower through-electrode; an interposer mounted on the lower semiconductor chip, the interposer including an interposer substrate; a plurality of interposer through-electrodes penetrating through at least a portion of the interposer substrate in a vertical direction and electrically connected to the lower through-electrode; and at least one capacitor in the interposer substrate and electrically connected to at least one interposer through-electrode of the plurality of interposer through-electrodes; and an upper semiconductor chip mounted on the interposer and electrically connected to the interposer through-electrode.

Abstract: An electronic system includes a first interposer including first signal paths, a second interposer spaced apart from the first interposer and including second signal paths, a first semiconductor chip structure on the first and second interposers and including a first circuit region and a second circuit region, and a second semiconductor chip structure on the first and second interposers and spaced apart from the first semiconductor chip structure. The second semiconductor chip structure includes a third circuit region configured to communicate with the first circuit region of the first semiconductor chip structure at a first rate through the first signal paths of the first interposer and a fourth circuit region configured to communicate with the second circuit region of the first semiconductor chip structure at a second rate, different from the first rate, through the second signal paths of the second interposer.

Abstract: Provided is a semiconductor package including a package substrate including a substrate pad, a first chip stacked structure including a first base chip mounted on an upper surface of the package substrate, and one or more first stacked chips sequentially offset-stacked along a first direction on the first base chip, a second chip stacked structure including a second base chip offset-stacked along the first direction on an upper surface of the first chip stacked structure, and one or more second stacked chips sequentially offset-stacked along the first direction on the second base chip, a bonding wire, and a first support mounted on the package substrate to be spaced apart from the first chip stacked structure in the first direction and supporting the second chip stacked structure, wherein the first support supports the second chip stacked structure by supporting a lower surface of the second base chip.

Abstract: A semiconductor package includes a processor, a lower memory including a plurality of lower memory chips that are vertically stacked, an interposer mounted on the processor and the lower memory, and an upper memory mounted on the interposer, the upper memory including a plurality of upper memory chips that are vertically stacked. The interposer includes a first physical layer (PHY) transmitting and receiving a signal between the processor and the lower memory and transmitting and receiving a signal between the processor and the upper memory, and the processor includes a second PHY communicating with the first PHY and a first through silicon via (TSV) electrically connecting the first PHY to the second PHY.

Abstract: Provided is a semiconductor package having improved signal integrity (SI) and a chip stack structure of a plurality of semiconductor chips. The semiconductor package includes a package substrate, a chip stack structure on the package substrate and including at least two semiconductor chips, and an external connection terminal on a lower surface of the package substrate. A first semiconductor chip arranged uppermost in the chip stack structure is connected to a first bonding pad of the package substrate through a first wire. A second semiconductor chip arranged under the first semiconductor chip in the chip stack structure is connected to a second bonding pad of the package substrate through a second wire. When the first bonding pad is farther from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate.

Abstract: A substrate is provided. The substrate includes a body layer that includes a signal area; a first wiring layer provided on a lower surface of the body layer, the first wiring layer including a plurality of first signal lines provided in the signal area and a first power line provided outside the signal area; and a second wiring layer provided on an upper surface of the body layer, the second wiring layer including a plurality of second signal lines provided in the signal area and a second power line provided outside the signal area.

Abstract: A semiconductor device and semiconductor package, the device including a lower semiconductor chip including a lower through-electrode; an interposer mounted on the lower semiconductor chip, the interposer including an interposer substrate; a plurality of interposer through-electrodes penetrating through at least a portion of the interposer substrate in a vertical direction and electrically connected to the lower through-electrode; and at least one capacitor in the interposer substrate and electrically connected to at least one interposer through-electrode of the plurality of interposer through-electrodes; and an upper semiconductor chip mounted on the interposer and electrically connected to the interposer through-electrode.

Abstract: A semiconductor package includes a processor, a lower memory including a plurality of lower memory chips that are vertically stacked, an interposer mounted on the processor and the lower memory, and an upper memory mounted on the interposer, the upper memory including a plurality of upper memory chips that are vertically stacked. The interposer includes a first physical layer (PHY) transmitting and receiving a signal between the processor and the lower memory and transmitting and receiving a signal between the processor and the upper memory, and the processor includes a second PHY communicating with the first PHY and a first through silicon via (TSV) electrically connecting the first PHY to the second PHY.