Patents by Inventor Ki-won Jo

Ki-won Jo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Voice recognition device, observation probability calculating device, complex fast fourier transform calculation device and method, cache device, and method of controlling the cache device
    Publication number: 20040002862
    Abstract: A voice recognition device including dedicated arithmetic calculating modules for arithmetic operations that are more frequently required among arithmetic operations necessary for voice recognition, an observation probability calculating device for calculating probabilities that each of the phonemes of a pre-selected word can be observed upon voice recognition, a complex Fast Fourier Transform (FFT) calculation device and method of calculating a complex FFT of complex data, a cache, and a cache controlling method are provided. The arithmetic modules interpret commands received from a receiver and perform operations indicated by the commands.
    Type: Application
    Filed: May 30, 2003
    Publication date: January 1, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jong-ho Kim, Hyun-woo Park, Tae-su Kim, Mi-jung Noh, Byung-ho Min, Ki-won Jo, Sung-hwan Jo, Seung-hwan Lee, Jin-won Jeong, Ho-rang Jang, Sun-hee Park, Keun-cheol Hong, Sung-jae Kim
  • Hybrid power supply circuit and method for charging/discharging a logic circuit using the same
    Patent number: 6542002
    Abstract: A hybrid power supply circuit for supplying a power to a logic circuit performing a digital logic process and for controlling the charging/discharging of the logic circuit. The power supply circuit has an adiabatic power supply portion for charging/discharging the logic circuit in such a manner to suppress a sudden current change during initial time after the input signal changes, and a CMOS power supply portion for quickly charging/discharging the logic circuit to supply power level/ground level after the charging/discharging by the adiabatic power supply portion. The energy consumption of the circuit decreases even in a digital system having a plurality of logic circuits.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: April 1, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-rang Jang, Ki-won Jo
  • Hybrid power supply circuit and method for charging/discharging a logic circuit using the same
    Publication number: 20020158660
    Abstract: A hybrid power supply circuit for supplying a power to a logic circuit performing a digital logic process and for controlling the charging/discharging of the logic circuit. The power supply circuit has an adiabatic power supply portion for charging/discharging the logic circuit in such a manner to suppress a sudden current change during initial time after the input signal changes, and a CMOS power supply portion for quickly charging/discharging the logic circuit to supply power level/ground level after the charging/discharging by the adiabatic power supply portion. The energy consumption of the circuit decreases even in a digital system having a plurality of logic circuits.
    Type: Application
    Filed: February 11, 2002
    Publication date: October 31, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ho-rang Jang, Ki-won Jo