Abstract: A semiconductor memory device includes a plurality of word lines, a first select gate line, a second select gate line, a first semiconductor layer, a third select gate line, a fourth select gate line, a second semiconductor layer, and a word line contact electrode. The first select gate line and the third select gate line are farther from the substrate than the plurality of word lines. The second select gate line and the fourth select gate line are closer to the substrate than the plurality of word lines. The first semiconductor layer is opposed to the plurality of word lines, the first select gate line, and the second select gate line. The second semiconductor layer is opposed to the plurality of word lines, the third select gate line, and the fourth select gate line. The word line contact electrode is connected to one of the plurality of word lines.

Abstract: A semiconductor memory device comprises a first exclusive-OR circuit which compares mth N-bit first data with (m+1)th N-bit second data, a majority circuit which generates flag data to invert the second data if a comparison result of the first exclusive-OR circuit indicates that the number of mismatch bits between the first data and the second data is not less than N/2, and generates flag data to noninvert the second data if the number of mismatch bits between the first data and the second data is less than N/2, a second exclusive-OR circuit which inverts or noninverts the second data based on the flag data, a shift register which stores the flag data generated by the majority circuit, and a pad to serially output both the inverted or noninverted second data and the flag data.

Abstract: A semiconductor memory device comprises a first exclusive-OR circuit which compares mth N-bit first data with (m+1)th N-bit second data, a majority circuit which generates flag data to invert the second data if a comparison result of the first exclusive-OR circuit indicates that the number of mismatch bits between the first data and the second data is not less than N/2, and generates flag data to noninvert the second data if the number of mismatch bits between the first data and the second data is less than N/2, a second exclusive-OR circuit which inverts or noninverts the second data based on the flag data, a shift register which stores the flag data generated by the majority circuit, and a pad to serially output both the inverted or noninverted second data and the flag data.

Abstract: A semiconductor integrated circuit includes a rectangular semiconductor chip having a main surface, a plurality of pads formed in a peripheral portion of the main surface of the semiconductor chip, for connection to external connecting members, a plurality of circuit elements of an integrated circuit formed in an area of the main surface other than an area in which the plurality of pads are formed, and at least one characteristic evaluating circuit element connected to at least one of the plurality of circuit elements of the integrated circuit by sharing an impurity doped region which forms part of the at least one circuit element with the at least one circuit element of the integrated circuit in an area of the main surface other than the peripheral portion in which the plurality of pads are formed.

Abstract: A semiconductor integrated circuit includes a rectangular semiconductor chip having a main surface, a plurality of pads formed in a peripheral portion of the main surface of the semiconductor chip, for connection to external connecting members, a plurality of circuit elements of an integrated circuit formed in an area of the main surface other than an area in which the plurality of pads are formed, and at least one characteristic evaluating circuit element connected to at least one of the plurality of circuit elements of the integrated circuit by sharing an impurity doped region which forms part of the at least one circuit element with the at least one circuit element of the integrated circuit in an area of the main surface other than the peripheral portion in which the plurality of pads are formed.