Patents by Inventor Kiyoaki Kadoi

Kiyoaki Kadoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230288454
    Abstract: A current detection device includes a main busbar and a semiconductor chip. A detected current flows through the main busbar. The semiconductor chip is spaced apart from the main busbar. The semiconductor chip includes a branch busbar, a detection part, and an output part. The branch busbar is connected in parallel with the main busbar. The detection part is arranged adjacent to the branch busbar and detects a first magnetic field generated based on a branch current flowing from the main busbar to the branch busbar. The output part calculates and outputs a current value based on the first magnetic field detected by the detection part.
    Type: Application
    Filed: March 7, 2023
    Publication date: September 14, 2023
    Applicant: ABLIC Inc.
    Inventor: Kiyoaki KADOI
  • Publication number: 20220254706
    Abstract: Provided a semiconductor device which is covered by an encapsulating resin into a cuboid shape, and has a plurality of lead portions partially exposed from side surfaces and a bottom surface thereof, the semiconductor device having cutout portions formed in the encapsulating resin along edges formed by the side surfaces and the bottom surface, each of the plurality of lead portions having a first exposed surface which is coplanar with one of the side surfaces, and is exposed from the one of the side surfaces; and second exposed surfaces which are surfaces that are adjacent to and on both sides of the first exposed surface, and are exposed from the one of the cutout portions.
    Type: Application
    Filed: January 4, 2022
    Publication date: August 11, 2022
    Inventor: Kiyoaki KADOI
  • Patent number: 11251110
    Abstract: In a semiconductor device (4), a semiconductor chip (10) is mounted on a die pad (6) which has a die pad overhang portion (6a) and leads (9) are arranged around and apart from the die pad (6). The leads (9) and the semiconductor chip (10) are electrically connected and are covered with a sealing resin (8). A concave portion (7e) is formed on the outer side of each lead (9), i.e., the far side from the die pad. A lead concave surface (7d) facing the concave portion (7e) includes a forward-tapered lead slope surface (7h). Side surface of the sealing resin (8) has a step of a staircase shape formed from the first and the second resin side surfaces (8a and 8b). A tip of the lead (9) protrudes past the first resin side surface (8a).
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: February 15, 2022
    Assignee: ABLIC INC.
    Inventor: Kiyoaki Kadoi
  • Publication number: 20200020617
    Abstract: Provided is a resin encapsulating mold by which deformation of tie bars of a lead frame is prevented during resin encapsulation. The resin encapsulating mold having a cavity by which a lead frame assembly having a semiconductor element is held and encapsulated with a resin to form a semiconductor device, includes protrusions (23) outside tie bar clamping portions (24a and 24b) formed around a cavity (22), to thereby prevent deformation of tie bars (2).
    Type: Application
    Filed: July 9, 2019
    Publication date: January 16, 2020
    Inventors: Yuta KIMURA, Kiyoaki KADOI, Yasuhiro TAGUCHI
  • Publication number: 20190279921
    Abstract: In a semiconductor device (4), a semiconductor chip (10) is mounted on a die pad (6) which has a die pad overhang portion (6a) and leads (9) are arranged around and apart from the die pad (6). The leads (9) and the semiconductor chip (10) are electrically connected and are covered with a sealing resin (8). A concave portion (7e) is formed on the outer side of each lead (9), i.e., the far side from the die pad. A lead concave surface (7d) facing the concave portion (7e) includes a forward-tapered lead slope surface (7h). Side surface of the sealing resin (8) has a step of a staircase shape formed from the first and the second resin side surfaces (8a and 8b). A tip of the lead (9) protrudes past the first resin side surface (8a).
    Type: Application
    Filed: January 17, 2019
    Publication date: September 12, 2019
    Inventor: Kiyoaki KADOI
  • Patent number: 10262924
    Abstract: Provided is a semiconductor device enabling highly accurate adjustment of a mounting height at a time when the semiconductor device is mounted on an assembly board, and an electronic apparatus. A linear lead is extracted from a bottom surface of a cylindrical resin sealing body covering a semiconductor chip, and a plurality of helical leads are arranged so as to wind around the linear lead, to thereby form a multi-helical structure. The plurality of helical leads forming the multi-helical structure has the same pitch.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 16, 2019
    Assignee: ABLIC INC.
    Inventor: Kiyoaki Kadoi
  • Publication number: 20180286786
    Abstract: Provided is a semiconductor device enabling highly accurate adjustment of a mounting height at a time when the semiconductor device is mounted on an assembly board, and an electronic apparatus. A linear lead is extracted from a bottom surface of a cylindrical resin sealing body covering a semiconductor chip, and a plurality of helical leads are arranged so as to wind around the linear lead, to thereby form a multi-helical structure. The plurality of helical leads forming the multi-helical structure has the same pitch.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 4, 2018
    Inventor: Kiyoaki KADOI
  • Publication number: 20170213775
    Abstract: Provided is a semiconductor device in which an internal pressure change in a cavity structure can be inspected. A semiconductor device (1), which is formed of a cavity-type package having a space in an inner part thereof, includes a pressure gauge (2), which enables inspection of a state of an internal space, and which is arranged on a surface of the semiconductor device (1). The pressure gauge (2) is formed of a plurality of straight lines intersecting each other at right angles, and whether there is an internal pressure change or not can be checked through measurement of a change in dimension between intersections.
    Type: Application
    Filed: January 23, 2017
    Publication date: July 27, 2017
    Inventor: Kiyoaki KADOI
  • Patent number: 7750443
    Abstract: A surface of a lead frame of a semiconductor device package, on which a semiconductor chip is mounted, is formed to have a mesh structure, whereby a connecting area between the lead frame and a molding resin can be increased to have strong bonding. Further, only filler particles having a small diameter than the mesh are taken into the vicinity of the lead frame, suppressing the effect of stresses to reduce deformation of the lead frame.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: July 6, 2010
    Assignee: Seiko Instruments Inc.
    Inventor: Kiyoaki Kadoi
  • Patent number: 7557016
    Abstract: A dicing blade (2) which rotates at high speed is surrounded by a case (3). A semiconductor wafer (1) is cut by a dicing device in which the case is filled with a cooling water (4). The case (3) is provided with a cooling water nozzle (8) for continuously supplying the cooling water and a gap (10) for discharging the cooling water out of the case. By adjusting a supply rate and a discharge rate of the cooling water, a proper water pressure can be applied to an inside of the case, thereby making it possible to cool the dicing blade and the cutting point with efficiency. As a result, it is possible to suppress chipping and cracking of the semiconductor device due to lack of cooling.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: July 7, 2009
    Assignee: Seiko Instruments Inc.
    Inventor: Kiyoaki Kadoi
  • Publication number: 20090026595
    Abstract: A surface of a lead frame of a semiconductor device package, on which a semiconductor chip is mounted, is formed to have a mesh structure, whereby a connecting area between the lead frame and a molding resin can be increased to have strong bonding. Further, only filler particles having a small diameter than the mesh are taken into the vicinity of the lead frame, suppressing the effect of stresses to reduce deformation of the lead frame.
    Type: Application
    Filed: July 23, 2008
    Publication date: January 29, 2009
    Inventor: Kiyoaki Kadoi
  • Publication number: 20070175466
    Abstract: A dicing blade (2) which rotates at high speed is surrounded by a case (3). A semiconductor wafer (1) is cut by a dicing device in which the case is filled with a cooling water (4). The case (3) is provided with a cooling water nozzle (8) for continuously supplying the cooling water and a gap (10) for discharging the cooling water out of the case. By adjusting a supply rate and a discharge rate of the cooling water, a proper water pressure can be applied to an inside of the case, thereby making it possible to cool the dicing blade and the cutting point with efficiency. As a result, it is possible to suppress chipping and cracking of the semiconductor device due to lack of cooling.
    Type: Application
    Filed: January 30, 2007
    Publication date: August 2, 2007
    Inventor: Kiyoaki Kadoi
  • Patent number: 6563216
    Abstract: In a semiconductor device, a metal wiring film and a lower-layer film under a bump electrode are patterned to form irregular steps under the bump electrode. With the formation of the irregular steps, the contact area of the bump electrode with a semiconductor substrate is increased to improve the mechanical strength. The lower-layer film is formed of a polysilicon film, an insulating film or a protective film such as a silicon nitride film, or Al—Si—Cu, Al—Si, Al—Cu or Cu. A portion where irregular steps are formed is in a region under the bump except for a protective film opening portion.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: May 13, 2003
    Assignee: Seiko Instruments Inc.
    Inventors: Noriyuki Kimura, Kiyoaki Kadoi
  • Patent number: 6492692
    Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: December 10, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Kazutoshi Ishii, Naoto Inoue, Koushi Maemura, Shoji Nakanishi, Yoshikazu Kojima, Kiyoaki Kadoi, Takao Akiba, Yasuhiro Moya, Kentaro Kuhara
  • Patent number: 6022792
    Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: February 8, 2000
    Assignee: Seiko Instruments, Inc.
    Inventors: Kazutoshi Ishii, Naoto Inoue, Koushi Maemura, Shoji Nakanishi, Yoshikazu Kojima, Kiyoaki Kadoi, Takao Akiba, Yasuhiro Moya, Kentaro Kuhara