Abstract: A latch group includes a first latch circuit, a second latch circuit, and a third latch circuit. A clock signal of which a signal value is inverted from a clock signal of the second latch circuit is input to the first latch circuit and the third latch circuit. A control circuit is configured to operate the latch group in a normal mode, and first and second test modes. The control circuit, while operating the latch group in a first test mode, transmits a control signal to the first switch circuit to connect the electrical path between the first data output terminal and the second data input terminal, and while operating the latch group in the second test mode, transmits a control signal to the second switch circuit to connect the electrical path between the second data output terminal and the third data input terminal.