Abstract: In a local module (11(1)) of an asynchronous time division exchange or switching system, each of connection ports (17) transfers a transmission signal to a module bus (19) as a cell with its header made to indicate a destination module number and a destination port number as a VCI (Virtual channel identifier) when the signal is directed to a destination module (11(N)) and one of the connection ports, respectively. Preferably, a connection control unit (15) of the local module transfers and does not transfer the cell to a highway bus (13) when the signal is directed to the destination module and the last-mentioned one of the connection ports. More preferably, the header additionally indicates a binary one and zero bit when the signal is directed to the destination module and the last-mentioned one of the connection ports.

Abstract: A terminal impedance setting circuit in a 2- to 4-wire converting circuit allows the characteristic impedance to be changed with accuracy while enhancing a miniaturization of the converting circuit. The impedance setting circuit has a first amplifier for amplifying signals that are incoming over a send pair of a four wire line and are destined for a two wire trunk line. A second amplifier amplifies signals that are incoming over the two wire trunk line and are destined for a receive pair of the four wire line. A resistor network is associated with each of the amplifiers for adjusting the output thereof. A shunt resistance is coupled between an input of the first amplifier and an output of the second amplifier for matching the impedance of the two wire trunk line. A semiconductor switch adjusts the resistances of the resistor networks and the shunt resistance in response to an external command.

Abstract: A control system attends to an orderly transmission of data over a time division multiplex data bus. Each time that a terminal wants to transmit data over the data bus, it files a request for data transmission with an arbiter circuit, which normally grants the requests on a first come, first serve basis. If there are simultaneous requests, the arbiter consults a table of priorities stored in its memory. The one of the simultaneous requests with the highest priority is served first.Each terminal acknowledges the data which it receives. If the acknowledgment does not come back in a timely manner, the data is retransmitted.