Abstract: A semiconductor integrated apparatus includes a control circuit unit which is connected to a low potential power supply terminal and a ground potential power supply terminal, and to which a predetermined low potential power supply output is supplied via the low potential power supply terminal, an output circuit unit which is connected to a high potential power supply terminal and the ground potential power supply terminal, and to which an output from the control circuit unit is supplied, and a detection circuit unit which is connected to the low potential power supply terminal, and which detects a decline in the predetermined low potential power supply output. The apparatus further includes a level shifter circuit which is provided between the control circuit unit and the output circuit unit, and which controls an output level of the output circuit unit in accordance with a detected output from the detection circuit unit.

Abstract: A semiconductor integrated circuit has a sense amplifier which senses and outputs data read out from memory cells connected to word lines and bit lines, and a read-out control circuit which has a standby state consuming minimum necessary power and a read state reading out the memory cells, and controls read-out of the memory cells, wherein the read-out control circuit includes, a bit line switching circuit which switches whether or not to transmit a potential on the bit line to an input terminal of the sense amplifier, and a first switching control circuit which controls the bit line switching circuit to prevent the potential on the bit line from being transmitted to the input terminal of the sense amplifier during a period of the standby state and a predetermined period after the standby state is released.

Abstract: One end of a fuse is connected to a ground point via a transistor N1A, and the other end thereof is connected to a node VaA. For example, at a fuse connection case, when INTV=“H” is input to the gate of the transistor N1A, the node VaA becomes “L.” At INTV=“L”, a transistor P1A having a low “on” resistance turns ON, and the node VaA is quickly precharged. At INTV=“H”, the transistor N1A turns ON, and the node VaA is quickly discharged.

Abstract: A memory data protection system is disclosed, which comprises a memory circuit, a protection contents indicating section which stores a security bit and a protection bit, a protection function circuit which determines permission/prohibition of reading of data from the memory circuit and permission/prohibition of writing of data to the memory circuit in accordance with the security bit and the protection bit, and a protection function locking/unlocking circuit which makes the protection function circuit in a lock state to forcibly prohibit reading of data from the memory circuit and writing of data into the memory circuit in a time period from when a power supply is turned on till when the protection function circuit completes reading of the security bit and the protection bit from the protection contents indicating section into data buses, and after lapse of the time period, the protection function locking/unlocking circuit unlocks the lock state.

Abstract: A semiconductor integrated apparatus includes a control circuit unit which is connected to a low potential power supply terminal and a ground potential power supply terminal, and to which a predetermined low potential power supply output is supplied via the low potential power supply terminal, an output circuit unit which is connected to a high potential power supply terminal and the ground potential power supply terminal, and to which an output from the control circuit unit is supplied, and a detection circuit unit which is connected to the low potential power supply terminal, and which detects a decline in the predetermined low potential power supply output. The apparatus further includes a level shifter circuit which is provided between the control circuit unit and the output circuit unit, and which controls an output level of the output circuit unit in accordance with a detected output from the detection circuit unit.

Abstract: A plurality of dummy cells which generate reference potential corresponding to a capacitance of a bit line each have a floating gate, control gate and first and second diffusion layers. The first and second diffusion layers of each dummy cell are commonly connected by use of a wiring.

Abstract: A semiconductor integrated circuit has a sense amplifier which senses and outputs data read out from memory cells connected to word lines and bit lines, and a read-out control circuit which has a standby state consuming minimum necessary power and a read state reading out the memory cells, and controls read-out of the memory cells, wherein the read-out control circuit includes, a bit line switching circuit which switches whether or not to transmit a potential on the bit line to an input terminal of the sense amplifier, and a first switching control circuit which controls the bit line switching circuit to prevent the potential on the bit line from being transmitted to the input terminal of the sense amplifier during a period of the standby state and a predetermined period after the standby state is released.

Abstract: A redundancy fuse circuit including a function of replacing a defective cell in a memory cell array with a redundancy cell, comprising a fuse circuit in which an address of the defective cell or a block including the defective cell is programmed as a defective address by presence/absence of cut-off of a fuse, a data latch circuit which latches a signal supplied from a tester to program the defective address in a dummy manner, and a comparator which replaces the defective cell with the redundancy cell based on an address signal supplied from the tester and an output signal of the data latch circuit at an operation confirmation time of the redundancy fuse circuit.

Abstract: A memory circuit device comprising a plurality of memory cells connected to a plurality of bit lines and word lines, an access circuit connected to the plurality of bit lines and word lines to select predetermined memory cells from the plurality of memory cells in response to an address signal, a precharge circuit which precharges the bit lines connected to the memory cells selected by the access circuit at the time of a read mode, a common source line connected to a plurality of selected memory cells selected by the access circuit, a source line potential control circuit to connect the common source line to a ground node at a predetermined timing, and a discharge circuit which discharges the bit lines connected to non-selected memory cells other than the selected memory cells.

Abstract: A plurality of dummy cells which generate reference potential corresponding to a capacitance of a bit line each have a floating gate, control gate and first and second diffusion layers. The first and second diffusion layers of each dummy cell are commonly connected by use of a wiring.

Abstract: A redundancy fuse circuit including a function of replacing a defective cell in a memory cell array with a redundancy cell, comprising a fuse circuit in which an address of the defective cell or a block including the defective cell is programmed as a defective address by presence/absence of cut-off of a fuse, a data latch circuit which latches a signal supplied from a tester to program the defective address in a dummy manner, and a comparator which replaces the defective cell with the redundancy cell based on an address signal supplied from the tester and an output signal of the data latch circuit at an operation confirmation time of the redundancy fuse circuit.

Abstract: One end of a fuse is connected to a ground point via a transistor N1A, and the other end thereof is connected to a node VaA. For example, at a fuse connection case, when INTV=“H” is input to the gate of the transistor N1A, the node VaA becomes “L.” At INTV=“L”, a transistor P1A having a low “on” resistance turns ON, and the node VaA is quickly precharged. At INTV=“H”, the transistor N1A turns ON, and the node VaA is quickly discharged.

Abstract: A memory circuit device comprising a plurality of memory cells connected to a plurality of bit lines and word lines, an access circuit connected to the plurality of bit lines and word lines to select predetermined memory cells from the plurality of memory cells in response to an address signal, a precharge circuit which precharges the bit lines connected to the memory cells selected by the access circuit at the time of a read mode, a common source line connected to a plurality of selected memory cells selected by the access circuit, a source line potential control circuit to connect the common source line to a ground node at a predetermined timing, and a discharge circuit which discharges the bit lines connected to non-selected memory cells other than the selected memory cells.

Abstract: A memory data protection system is disclosed, which comprises a memory circuit, a protection contents indicating section which stores a security bit and a protection bit, a protection function circuit which determines permission/prohibition of reading of data from the memory circuit and permission/prohibition of writing of data to the memory circuit in accordance with the security bit and the protection bit, and a protection function locking/unlocking circuit which makes the protection function circuit in a lock state to forcibly prohibit reading of data from the memory circuit and writing of data into the memory circuit in a time period from when a power supply is turned on till when the protection function circuit completes reading of the security bit and the protection bit from the protection contents indicating section into data buses, and after lapse of the time period, the protection function locking/unlocking circuit unlocks the lock state.

Abstract: A semiconductor memory device includes a memory cell array, a read control circuit, a row decoder, a column decoder, a sense amplifier, and a sense amplifier control circuit. The read control circuit produces a precharge signal to precharge a bit line of the memory cell array. The sense amplifier amplifies data read onto the bit line. In reading data from a memory cell, the sense amplifier control circuit enables the sense amplifier and inhibits entry of read data from a memory cell into the sense amplifier only for a fixed interval after a fixed time after the precharging signal has been negated. The sense amplifier control circuit allows entry of read data into the sense amplifier while the sense amplifier is being disabled.

Abstract: A semiconductor memory device includes a memory cell array, a read control circuit, a row decoder, a column decoder, a sense amplifier, and a sense amplifier control circuit. The read control circuit produces a precharge signal to precharge a bit line of the memory cell array. The sense amplifier amplifies data read onto the bit line. In reading data from a memory cell, the sense amplifier control circuit enables the sense amplifier and inhibits entry of read data from a memory cell into the sense amplifier only for a fixed interval after a fixed time after the precharging signal has been negated. The sense amplifier control circuit allows entry of read data into the sense amplifier while the sense amplifier is being disabled.

Abstract: A semiconductor device has a circuit board, a main chip mounted on a first surface of the circuit board, a subchip mounted on a second surface of the circuit board, interface circuits distributed in the main chip along four sides of the main chip, respectively, to interface the main chip and the subchip with each other, subchip connecting terminals for connecting the interface circuits and the subchip to each other through the circuit board, main-chip connecting terminals for connecting the main chip and the outside to each other, subchip bonding terminals connected to the subchip, a first wiring area for connecting the subchip bonding terminals and the subchip connecting terminals to each other, package terminals for connecting the main chip and the outside to each other, and a second wiring area for connecting the package terminals and the main-chip connecting terminals to each other.

Abstract: An MCP has an MCP substrate, first and second semiconductor chips mounted on the MCP substrate, MCP leads connected to perimeter of the MCP substrate. MCP terminal wires disposed on the MCP substrate connect the MCP leads to the first semiconductor chip. Interface signal wires disposed on the MCP substrate connect the first and second semiconductor chips to each other. The MCP further has first and second extra bonding pads. The first extra bonding pad electrically connects to the interface signal wires. The second extra bonding pad electrically connects to the MCP leads. The second extra bonding pad is arranged near the first extra bonding pad. The first and second extra bonding pads are designed to be electrically isolated from each other in a normal usage condition. However, the first and second extra bonding pads are electrically connected to each other when failure analysis is required.

Abstract: A bank register circuit for an MAC employs compact bank registers and involves a short read time for transferring data to a system bus. The bank register circuit has a dedicated write bus (5), a dedicated read bus (6), and an interface (7) between the bank registers (2, 3) and the system bus (4), to transfer data between the bank registers (2, 3) and the system bus (4).

Abstract: An inverter circuit according to this invention includes n- and p-type field effect transistors having predetermined wiring resistances and gates and drains connected with each other, a first power source connected to the source of the n-type field effect transistor, a power source connected to the source of the p-type field effect transistor, and first and second negative feedback switching transistors connected in parallel between the gates and the drains of the n- and p-type field effect transistors. Assuming that the channel length and width of the first insulating gate field effect transistor are L.sub.N and W.sub.N, respectively, and the wiring resistance thereof is R.sub.S, that the channel length and width of the second insulating gate field effect transistor are L.sub.P and W.sub.P, respectively, and the wiring resistance thereof is R.sub.D, and that carrier mobilities of the first and second insulating gate field effect transistors are .mu..sub.N and .mu..sub.