Abstract: To provide a data transmitting apparatus and the like capable of enhancing error detection accuracy without increasing a bandwidth unnecessarily used for the error detection performed on encrypted data and minimizing deterioration in sound quality of the data by effectively reducing noises in the transmission of the data through networks for cars and the like even though the data transmitting apparatus has been simply structured. The present invention makes it possible to perform error detection on audio data according to the sizes of encrypted blocks or packets using simple error check codes embedded in the audio data, or to perform error detection using a variation sequence of attribute information to be transmitted together with the audio data. In this case, output of the sound resulting from the audio data having an error is stopped.

Abstract: An address output apparatus capable of retaining a pre-extension upper compatibility of software post memory extension and of accessing separated RAM areas by consecutive addresses, without needing to alter CPU architecture. The address output apparatus includes an address conversion circuit 20 that allots to a RAM 30 a basic RAM area and a first area, being one of two area obtained by dividing an extension RAM area, allots to a RAM 50 a second area, being an area other than the first area of the extension RAM area, and converts logical address signals designated by a CPU 10 to physical address signals based on a state of the allotting.

Abstract: An address output apparatus capable of retaining a pre-extension upper compatibility of software post memory extension and of accessing separated RAM areas by consecutive addresses, without needing to alter CPU architecture. The address output apparatus includes an address conversion circuit 20 that allots to a RAM 30 a basic RAM area and a first area, being one of two area obtained by dividing an extension RAM area, allots to a RAM 50 a second area, being an area other than the first area of the extension RAM area, and converts logical address signals designated by a CPU 10 to physical address signals based on a state of the allotting.