Abstract: A non-volatile semiconductor memory device comprising: a semiconductor substrate, memory cells, a region of memory cell array in which said memory cells are arranged in a matrix-like form, a region of peripheral circuit, a connecting region for connecting said region of memory cell array to said region of peripheral circuit, and conductive layers provided closest to said substrate with intervals between each other, wherein said intervals of said conductive layers are substantially equal to each other in said region of memory cell array and said connecting region, whereby when insulating films are formed and planarized after forming said conductive layers, it is possible to restrict producing of seams in the insulating films at stripped portions of the conductive layers.

Abstract: In a non-volatile semiconductor memory device according to the present invention, a p type source region and a p type drain region are formed in the surface of an n well. A floating gate electrode and a control gate electrode are formed on a channel region with a tunnel oxide film interposed therebetween. According to this structure, a negative potential is applied to the drain region and a positive potential is applied to the control gate electrode when data is programmed, whereby electrons are injected from the drain region to the floating gate electrode by a band-to-band tunnel current induced hot electron injection current in the drain region. As a result, a non-volatile semiconductor memory device is provided which can prevent deterioration of the tunnel oxide film and which can be miniaturized.

Abstract: Under an N.sup.- -drain region covering an N.sup.+ -drain region, a P.sup.+ -impurity region is formed without covering an end of the N.sup.- -drain region near a channel region. Thereby, the P.sup.+ -impurity region suppresses a punch-through phenomenon, while the N.sup.- -drain region prevents a leak current due to interband tunneling.

Abstract: In a non-volatile semiconductor memory device according to the present invention, a p type source region and a p type drain region are formed in the surface of an n well. A floating gate electrode and a control gate electrode are formed on a channel region with a tunnel oxide film interposed therebetween. According to this structure, a negative potential is applied to the drain region and a positive potential is applied to the control gate electrode when data is programmed, whereby electrons are injected from the drain region to the floating gate electrode by a band-to-band tunnel current induced hot electron injection current in the drain region. As a result, a non-volatile semiconductor memory device is provided which can prevent deterioration of the tunnel oxide film and which can be miniaturized.

Abstract: Under an N.sup.- -drain region covering an N.sup.+ -drain region, a P.sup.+ -impurity region is formed without covering an end of the N.sup.- -drain region near a channel region. Thereby, the P.sup.+ -impurity region suppresses a punch-through phenomenon, while the N.sup.- -drain region prevents a leak current due to interband tunneling.

Abstract: It is postulated that a nonvolatile semiconductor memory device of the present invention includes a charge pump. The nonvolatile semiconductor memory device includes a memory cell array unit having a plurality of memory transistors formed therein to store data. Each memory transistor has a drain region connected to a predetermined bit line BL which is connected to a write circuit. A charge pump is connected to the write circuit. A predetermined potential is applied to a memory transistor via the write circuit by this charge pump in a writing mode. A charge pump load control means for suppressing variation in the charge pump load is connected to a memory transistor or a well region in which the memory transistor is formed. Thus, the charge pump load can be stabilized to allow improvement of the writing or erasing characteristics of the nonvolatile semiconductor memory device.

Abstract: A charge coupled device includes a second conductivity type first horizontal channel in a first conductivity type semiconductor substrate, a second conductivity type second horizontal channel in the substrate at a predetermined distance from the first horizontal channel, and a second conductivity type transfer channel connecting the first horizontal channel with the second horizontal channel to enable transfer of charges from the first horizontal channel to the second horizontal channel. The pinning potential of the transfer channel is larger in absolute value than the pinning potential of the first and second horizontal channels, and the gate voltage pinning the transfer channel is smaller in absolute value than the gate voltage pinning the first and second horizontal channels.

Abstract: A method for producing a solid-state imaging device including a photodetector including implanting two different dopant impurity ions, each producing the second conductivity type and having different diffusion coefficients in a first conductivity type semiconductor layer; thermally diffusing the implanted ions to produce a second conductivity type region including a relatively deep second conductivity type subregion and a relatively shallow second conductivity type region having a higher dopant impurity concentration than said relatively deep second conductivity type subregion; forming a charge transfer electrode on said semiconductor layer such that an edge of said electrode lies adjacent part of the junction between said semiconductor layer and said second conductivity type region; and implanting a dopant impurity producing the first conductivity type in said second relatively shallow second conductivity type subregion using said charge transfer electrode as a mask to produce a first conductivity type impur

Abstract: A solid-state imaging device includes a photodetector having a first conductivity type semiconductor layer, a second conductivity type semiconductor region in the layer, and a first conductivity type region in the second conductivity type region. The second conductivity type semiconductor region includes second conductivity type subregions having different dopant impurity concentrations. The subregion which contacts the first conductivity type region has a dopant impurity concentration higher than the second conductivity type subregion. The device reads out photogenerated charges stored in the second conductivity type region as a light signal. The junction capacitances between the second conductivity type semiconductor region and the first conductivity type layer and the first conductivity type region are increased so that the maximum quantity of stored charge when the first conductivity type region is depleted is increased without a change in the potential.

Abstract: A charge coupled device includes a second conductivity type first horizontal channel in a first conductivity type semiconductor substrate, a second conductivity type second horizontal channel in the substrate at a predetermined distance from the first horizontal channel, and a second conductivity type transfer channel connecting the first horizontal channel with the second horizontal channel to enable transfer of charges from the first horizontal channel to the second horizontal channel. The pinning potential of the transfer channel is larger in absolute value than the pinning potential of the first and second horizontal channels, and the gate voltage pinning the transfer channel is smaller in absolute value than the gate voltage pinning the first and second horizontal channels.