Patents by Inventor Kiyohiko Sato

Kiyohiko Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200027920
    Abstract: To provide a magnetic tunnel junction (MTJ) element that is adapted to suppress the degradation of magnetic properties of a magnetic tunnel junction layer due to plasma CVD layer formation and adapted for miniaturization. The MTJ element includes a magnetic tunnel junction layer (101, 102, 103) and a plurality of passivation layers formed on a side wall of the magnetic tunnel junction layer. The plurality of passivation layers are SiN layers formed under different plasma CVD layer forming conditions and include a first passivation layer 109 formed in direct contact with the magnetic tunnel junction layer. A hydrogen ion density or hydrogen ion energy of a layer forming condition for the first passivation layer is lower than a hydrogen ion density or hydrogen ion energy of a layer forming condition for the other of the plural passivation layers. The other passivation layers include a passivation layer, a nitrogen density of which is higher than a nitrogen density of the first passivation layer.
    Type: Application
    Filed: February 27, 2019
    Publication date: January 23, 2020
    Inventors: Katsuya MIURA, Hirotaka HAMAMURA, Yu ZHAO, Masaki YAMADA, Kiyohiko SATO
  • Publication number: 20200006644
    Abstract: Provided is a method of manufacturing a magnetic tunnel junction that simultaneously realizes removal of oxides on side walls of a magnetic layer and formation of a protective film and prevents deterioration of magnetic characteristics. The method includes: a first step 802 of etching a stacked film including a first magnetic layer, a MgO barrier layer, and a second magnetic layer stacked in order by plasma etching using an oxidizing gas to form the magnetic tunnel junction; and a second step 803 of simultaneously introducing an organic acid gas which is an n-valent acid and a precursor gas having a corresponding metal element valence of m, to form a first protective film on side walls of the magnetic tunnel junction. In the second step, the precursor gas is introduced at a molar ratio of n/m or more with respect to 1 mole of the organic acid gas introduced.
    Type: Application
    Filed: January 7, 2019
    Publication date: January 2, 2020
    Inventors: Yu ZHAO, Katsuya MIURA, Hirotaka HAMAMURA, Masaki Yamada, Kiyohiko SATO
  • Patent number: 8933514
    Abstract: The orientation polarization (positive and negative) of the Si—N bonds and the Si—O bonds is canceled, thereby enabling to minimize the polarization in a capacitive insulating film. As a result, a silicon oxynitride film with a small voltage secondary coefficient is formed, and is applied as a capacitive insulating film for use in a MIM capacitor. Specifically, the refractive index “n” of the silicon oxynitride film satisfies 1.47?n?1.53, for light with a wavelength of 633 nm.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: January 13, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Kiyohiko Sato, Ryohei Maeno, Tsuyoshi Fujiwara, Akira Otaguro, Yukino Ishii, Kiyomi Katsuyama, Hidenori Sato, Daichi Matsumoto
  • Publication number: 20110291280
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 1, 2011
    Inventors: Kazutoshi OHMORI, Tsuyoshi TAMARU, Naohumi OHASHI, Kiyohiko SATO, Hiroyuki MARUYAMA
  • Patent number: 8012871
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: September 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Publication number: 20100210107
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Application
    Filed: April 30, 2010
    Publication date: August 19, 2010
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Patent number: 7723849
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: May 25, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Publication number: 20070105369
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Application
    Filed: December 28, 2006
    Publication date: May 10, 2007
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Patent number: 7176121
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: February 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Publication number: 20040192032
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Application
    Filed: October 15, 2003
    Publication date: September 30, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Publication number: 20040152336
    Abstract: Disclosed here is a method for manufacturing a semiconductor device, which can prevent films from delamination and improve the reliability of the semiconductor. A first insulating film comprising a silicon carbide film, silicon carbide nitride film, or silicon oxide nitride film is formed as a barrier insulating film of the wiring, and then a second insulating film comprising a fluorine containing silicon oxide film is formed on the first insulating film by a high density plasma CVD method as a low permittivity insulating film. And, when forming the second insulating film, the semiconductor substrate is heated up to a predetermined deposition temperature using a heat-up plasma generated by a gas containing no oxygen such as an argon plasma. When the substrate reaches the predetermined deposition temperature, the insulating film deposition gas is introduced into the deposition chamber to deposit the second insulating film on the first insulating film.
    Type: Application
    Filed: January 7, 2004
    Publication date: August 5, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Noriko Miura, Kazutoshi Ohmori, Kiyohiko Sato, Junji Noguchi, Tsuyoshi Tamaru
  • Patent number: 6368062
    Abstract: The spring-back state of the blade press formed from the metallic thin plate is restricted to form the blade of wing sectional shape strictly in accordance with the design. The blade is formed into the wing sectional shape having a hollow inner part with both sides fixed to the upper plate and the lower plate being released under application of the press forming of the metallic thin plate.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: April 9, 2002
    Assignee: Fuji Industrial Co., Ltd.
    Inventors: Mototake Yagami, Kiyohiko Sato
  • Patent number: 5357166
    Abstract: In a cathode-ray tube, in order to readily and inexpensively reduce an alternating electric field irradiated by a deflection yoke to a front of the cathode-ray tube through a funnel part and a face panel, a conductive film for forming an electric field shield is formed from a neck part to a cone part of a glass bulb and is electrically connected to another conductive film formed on a funnel body part. The deflection yoke is mounted on the conductive film via an insulation sheet interposed therebetween. The conductive film is grounded to form an equipotential surface of 0 V in front of the deflection yoke. A transparent conductive film can be also formed on the external surface of the face panel to raise the reduction of the alternating electric field.
    Type: Grant
    Filed: April 17, 1992
    Date of Patent: October 18, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Sugahara, Kiyohiko Sato
  • Patent number: 5122819
    Abstract: A compound corrective lens for use in light exposure in the manufacture of color CRTs includes plurality of lens elements, each having an elementary surface, formed in combination a compound surface on the exit side of the lens, with steps formed at the boundaries between adjacent lens elements to connect edges of the elementary surfaces of the adjacent lens elements. The surfaces are so arranged that the steps falls from the elementary surface on the inner side closest to the optical axis of the lens) to the elementary surface on the outer side (farthest from the optical axis). With such an arrangement, the adverse effect of the steps covered with a light-absorbing layer is reduced. That is, the effective areas of the elementary surfaces are enlarged, and thus the distortion of the lens surface is suppressed.
    Type: Grant
    Filed: October 18, 1991
    Date of Patent: June 16, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kiyohiko Sato