Patents by Inventor Kiyohiko Sato
Kiyohiko Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11776792Abstract: A plasma processing apparatus or a plasma processing method having an improved yield, the plasma processing apparatus includes: a processing chamber arranged inside a vacuum container; a processing gas supply line connecting to the vacuum container, communicating with the processing chamber, and configured to supply processing gas having adhesiveness to the processing chamber; and a gas exhaust line for the processing gas connecting and communicating the processing gas supply line with a processing chamber exhaust line that is connected to an exhaust pump and communicates with the processing chamber, in which the plasma processing apparatus exhausts the processing gas in the processing gas supply line through the gas exhaust line and the processing chamber exhaust line in a state where supplying of the processing gas to the processing chamber is stopped between one processing step of etching the wafer and a subsequent processing step.Type: GrantFiled: April 3, 2020Date of Patent: October 3, 2023Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Shunsuke Tashiro, Takashi Uemura, Shengnan Yu, Yasushi Sonoda, Kiyohiko Sato, Masahiro Nagatani
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Patent number: 11678583Abstract: Provided is a method of manufacturing a magnetic tunnel junction that simultaneously realizes removal of oxides on side walls of a magnetic layer and formation of a protective film and prevents deterioration of magnetic characteristics. The method includes: a first step 802 of etching a stacked film including a first magnetic layer, a MgO barrier layer, and a second magnetic layer stacked in order by plasma etching using an oxidizing gas to form the magnetic tunnel junction; and a second step 803 of simultaneously introducing an organic acid gas which is an n-valent acid and a precursor gas having a corresponding metal element valence of m, to form a first protective film on side walls of the magnetic tunnel junction. In the second step, the precursor gas is introduced at a molar ratio of n/m or more with respect to 1 mole of the organic acid gas introduced.Type: GrantFiled: February 1, 2022Date of Patent: June 13, 2023Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Yu Zhao, Katsuya Miura, Hirotaka Hamamura, Masaki Yamada, Kiyohiko Sato
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Publication number: 20230027528Abstract: A semiconductor manufacturing method using a semiconductor manufacturing apparatus 100 including a treating chamber 1, the method including: a first process of supplying a complexing gas into the treating chamber in which a wafer 2 having a surface having a transition metal-containing film formed thereon is placed, to adsorb an organic compound as a component of the complexing gas to the transition metal-containing film, the transition metal-containing film containing a transition metal element; and a second process of heating the wafer in which the organic compound is adsorbed to the transition metal-containing film, to react the organic compound with the transition metal element, thereby converting the organic compound into an organometallic complex, and desorbing the organometallic complex, wherein the organic compound has Lewis basicity, and is a multidentate ligand molecule capable of forming a bidentate or more coordination bond with the transition metal element.Type: ApplicationFiled: December 10, 2020Publication date: January 26, 2023Inventors: Yoshihide Yamaguchi, Kiyohiko Sato
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Publication number: 20220158088Abstract: Provided is a method of manufacturing a magnetic tunnel junction that simultaneously realizes removal of oxides on side walls of a magnetic layer and formation of a protective film and prevents deterioration of magnetic characteristics. The method includes: a first step 802 of etching a stacked film including a first magnetic layer, a MgO barrier layer, and a second magnetic layer stacked in order by plasma etching using an oxidizing gas to form the magnetic tunnel junction; and a second step 803 of simultaneously introducing an organic acid gas which is an n-valent acid and a precursor gas having a corresponding metal element valence of m, to form a first protective film on side walls of the magnetic tunnel junction. In the second step, the precursor gas is introduced at a molar ratio of n/m or more with respect to 1 mole of the organic acid gas introduced.Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Inventors: Yu Zhao, Katsuya Miura, Hirotaka Hamamura, Masaki Yamada, Kiyohiko Sato
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Publication number: 20220115212Abstract: A plasma processing apparatus or a plasma processing method having an improved yield, the plasma processing apparatus includes: a processing chamber arranged inside a vacuum container; a processing gas supply line connecting to the vacuum container, communicating with the processing chamber, and configured to supply processing gas having adhesiveness to the processing chamber; and a gas exhaust line for the processing gas connecting and communicating the processing gas supply line with a processing chamber exhaust line that is connected to an exhaust pump and communicates with the processing chamber, in which the plasma processing apparatus exhausts the processing gas in the processing gas supply line through the gas exhaust line and the processing chamber exhaust line in a state where supplying of the processing gas to the processing chamber is stopped between one processing step of etching the wafer and a subsequent processing step.Type: ApplicationFiled: April 3, 2020Publication date: April 14, 2022Inventors: Shunsuke Tashiro, Takashi Uemura, Shengnan Yu, Yasushi Sonoda, Kiyohiko Sato, Masahiro Nagatani
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Patent number: 11276816Abstract: Provided is a method of manufacturing a magnetic tunnel junction that simultaneously realizes removal of oxides on side walls of a magnetic layer and formation of a protective film and prevents deterioration of magnetic characteristics. The method includes: a first step 802 of etching a stacked film including a first magnetic layer, a MgO barrier layer, and a second magnetic layer stacked in order by plasma etching using an oxidizing gas to form the magnetic tunnel junction; and a second step 803 of simultaneously introducing an organic acid gas which is an n-valent acid and a precursor gas having a corresponding metal element valence of m, to form a first protective film on side walls of the magnetic tunnel junction. In the second step, the precursor gas is introduced at a molar ratio of n/m or more with respect to 1 mole of the organic acid gas introduced.Type: GrantFiled: January 7, 2019Date of Patent: March 15, 2022Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Yu Zhao, Katsuya Miura, Hirotaka Hamamura, Masaki Yamada, Kiyohiko Sato
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Patent number: 11164906Abstract: To provide a magnetic tunnel junction (MTJ) element that is adapted to suppress the degradation of magnetic properties of a magnetic tunnel junction layer due to plasma CVD layer formation and adapted for miniaturization. The MTJ element includes a magnetic tunnel junction layer (101, 102, 103) and a plurality of passivation layers formed on a side wall of the magnetic tunnel junction layer. The plurality of passivation layers are SiN layers formed under different plasma CVD layer forming conditions and include a first passivation layer 109 formed in direct contact with the magnetic tunnel junction layer. A hydrogen ion density or hydrogen ion energy of a layer forming condition for the first passivation layer is lower than a hydrogen ion density or hydrogen ion energy of a layer forming condition for the other of the plural passivation layers. The other passivation layers include a passivation layer, a nitrogen density of which is higher than a nitrogen density of the first passivation layer.Type: GrantFiled: February 27, 2019Date of Patent: November 2, 2021Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Katsuya Miura, Hirotaka Hamamura, Yu Zhao, Masaki Yamada, Kiyohiko Sato
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Publication number: 20210082766Abstract: In a manufacturing process of a three-dimensional structure device such as a GAA type FET or a nanosheet fork type FET having stacked channels in which channels having a shape of a wire or a sheet are stacked in a direction vertical to a substrate, a work function control metal is separately formed without expanding a space between FETs having different threshold voltages. Therefore, a first step S10 of performing anisotropic etching to open the mask material 23 until the work function control metal film 22 is exposed; a second step S11 of depositing a protective film 26; a third step S12 of performing anisotropic etching to remove the protective film while remaining the protective film deposited on sidewalls of the mask material opened in the first step; and a fourth step S13 of performing isotropic etching to selectively remove the mask material between the channels relative to the protective film and the work function control metal film are executed.Type: ApplicationFiled: September 13, 2019Publication date: March 18, 2021Applicant: Hitachi High-Tech CorporationInventors: Makoto Miura, Kiyohiko Sato, Yasushi Sonoda, Satoshi Sakai
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Publication number: 20200027920Abstract: To provide a magnetic tunnel junction (MTJ) element that is adapted to suppress the degradation of magnetic properties of a magnetic tunnel junction layer due to plasma CVD layer formation and adapted for miniaturization. The MTJ element includes a magnetic tunnel junction layer (101, 102, 103) and a plurality of passivation layers formed on a side wall of the magnetic tunnel junction layer. The plurality of passivation layers are SiN layers formed under different plasma CVD layer forming conditions and include a first passivation layer 109 formed in direct contact with the magnetic tunnel junction layer. A hydrogen ion density or hydrogen ion energy of a layer forming condition for the first passivation layer is lower than a hydrogen ion density or hydrogen ion energy of a layer forming condition for the other of the plural passivation layers. The other passivation layers include a passivation layer, a nitrogen density of which is higher than a nitrogen density of the first passivation layer.Type: ApplicationFiled: February 27, 2019Publication date: January 23, 2020Inventors: Katsuya MIURA, Hirotaka HAMAMURA, Yu ZHAO, Masaki YAMADA, Kiyohiko SATO
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Publication number: 20200006644Abstract: Provided is a method of manufacturing a magnetic tunnel junction that simultaneously realizes removal of oxides on side walls of a magnetic layer and formation of a protective film and prevents deterioration of magnetic characteristics. The method includes: a first step 802 of etching a stacked film including a first magnetic layer, a MgO barrier layer, and a second magnetic layer stacked in order by plasma etching using an oxidizing gas to form the magnetic tunnel junction; and a second step 803 of simultaneously introducing an organic acid gas which is an n-valent acid and a precursor gas having a corresponding metal element valence of m, to form a first protective film on side walls of the magnetic tunnel junction. In the second step, the precursor gas is introduced at a molar ratio of n/m or more with respect to 1 mole of the organic acid gas introduced.Type: ApplicationFiled: January 7, 2019Publication date: January 2, 2020Inventors: Yu ZHAO, Katsuya MIURA, Hirotaka HAMAMURA, Masaki Yamada, Kiyohiko SATO
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Patent number: 8933514Abstract: The orientation polarization (positive and negative) of the Si—N bonds and the Si—O bonds is canceled, thereby enabling to minimize the polarization in a capacitive insulating film. As a result, a silicon oxynitride film with a small voltage secondary coefficient is formed, and is applied as a capacitive insulating film for use in a MIM capacitor. Specifically, the refractive index “n” of the silicon oxynitride film satisfies 1.47?n?1.53, for light with a wavelength of 633 nm.Type: GrantFiled: January 25, 2013Date of Patent: January 13, 2015Assignee: Hitachi, Ltd.Inventors: Kiyohiko Sato, Ryohei Maeno, Tsuyoshi Fujiwara, Akira Otaguro, Yukino Ishii, Kiyomi Katsuyama, Hidenori Sato, Daichi Matsumoto
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Publication number: 20110291280Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: ApplicationFiled: August 10, 2011Publication date: December 1, 2011Inventors: Kazutoshi OHMORI, Tsuyoshi TAMARU, Naohumi OHASHI, Kiyohiko SATO, Hiroyuki MARUYAMA
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Patent number: 8012871Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: GrantFiled: April 30, 2010Date of Patent: September 6, 2011Assignee: Renesas Electronics CorporationInventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
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Publication number: 20100210107Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: ApplicationFiled: April 30, 2010Publication date: August 19, 2010Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
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Patent number: 7723849Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: GrantFiled: December 28, 2006Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
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Publication number: 20070105369Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: ApplicationFiled: December 28, 2006Publication date: May 10, 2007Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
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Patent number: 7176121Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: GrantFiled: October 15, 2003Date of Patent: February 13, 2007Assignee: Renesas Technology Corp.Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
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Publication number: 20040192032Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: ApplicationFiled: October 15, 2003Publication date: September 30, 2004Applicant: Renesas Technology Corp.Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
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Publication number: 20040152336Abstract: Disclosed here is a method for manufacturing a semiconductor device, which can prevent films from delamination and improve the reliability of the semiconductor. A first insulating film comprising a silicon carbide film, silicon carbide nitride film, or silicon oxide nitride film is formed as a barrier insulating film of the wiring, and then a second insulating film comprising a fluorine containing silicon oxide film is formed on the first insulating film by a high density plasma CVD method as a low permittivity insulating film. And, when forming the second insulating film, the semiconductor substrate is heated up to a predetermined deposition temperature using a heat-up plasma generated by a gas containing no oxygen such as an argon plasma. When the substrate reaches the predetermined deposition temperature, the insulating film deposition gas is introduced into the deposition chamber to deposit the second insulating film on the first insulating film.Type: ApplicationFiled: January 7, 2004Publication date: August 5, 2004Applicant: Renesas Technology Corp.Inventors: Noriko Miura, Kazutoshi Ohmori, Kiyohiko Sato, Junji Noguchi, Tsuyoshi Tamaru
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Patent number: 6368062Abstract: The spring-back state of the blade press formed from the metallic thin plate is restricted to form the blade of wing sectional shape strictly in accordance with the design. The blade is formed into the wing sectional shape having a hollow inner part with both sides fixed to the upper plate and the lower plate being released under application of the press forming of the metallic thin plate.Type: GrantFiled: July 11, 2000Date of Patent: April 9, 2002Assignee: Fuji Industrial Co., Ltd.Inventors: Mototake Yagami, Kiyohiko Sato