Abstract: A timing control circuit includes a synchronous detecting portion which detects a synchronous pattern data of a received signal which has been demodulated based on a first control signal and generates a detection result, a first counter portion which generates a first signal at each first cycle based on the detection result, a second counter portion which generates a second signal at each second cycle based on the detection result, and a first control portion which generates the first control signal based on the first and second signals.

Abstract: An apparatus for decoding encoded voice data comprises a demodulator (101) which demodulates the encoded voice data (RF) and provides a demodulated encoded voice data (APO, RD), an adaptive differential pulse code modulation decoder (102) which decodes the demodulated encoded voice data and provides a pulse code modulation data (PO), an error detector (103) which detects whether error is present in the encoded voice data based on the demodulated encoded voice data and outputs a detection result (CRCERR) and a limiter (104) which outputs either the pulse code modulation data (POL) or a limit data (POL) in accordance with the detection result (CRCERR).

Abstract: Disclosed herein is a receiving circuit comprising demodulator 101 which pulls in the phase of each of burst signals respectively having preambles 701 and 711 each storing phase information or data therein, synchronous pattern parts 702 and 712 each storing synchronous information therein, and data parts 703 and 713 each storing the data therein, and outputs data obtained by demodulating the burst signal, a controller 110 which performs counting based on the demodulated data to output a timing signal, and a storage unit 102 which stores or outputs the demodulated data, based on the timing signal.

Abstract: A pulse generator is provided which operates as a counter capable of resetting a count according to an instruction signal for providing instructions for the detection of a synchronizing pattern from a previously received burst signal having some of continuous pseudo random patterns. The pulse generator performs counting up to timing provided to detect a synchronizing pattern of a burst signal having a continuous part of a pseudo random pattern to be consecutively received and thereby outputs a count-up signal CO similar to the instruction signal.

Abstract: A communication channel selecting circuit which can select and use a channel that does not disturb or interfere with another radio apparatus, avoiding a channel occupied by other similar radio apparatus nearby, is provided. The communication channel selecting circuit selects a communication channel in accordance with radio signal intensity, the selecting circuit transmitting and receiving radio signals in a plurality of channels. A radio unit outputs a signal indicating radio signal intensity of a radio signal received through an antenna in a receiving status and transmitting a radio signal to the antenna in a transmission status. A control circuit sets the radio unit to the receiving status even at a transmission timing.

Abstract: Radio apparatus is capable of quantitatively evaluating the improvement in the quality of received signals. A receiving circuit selects the evaluation mode in a mode selection circuit and transfers demodulated digital signals to an error generator. The digital signals are inverted in level by an Ex-OR gate circuit, using a predetermined timing supplied from a counter, to define an error condition, to transmit digital signals containing error data via a mode selection circuit to a error detector and a data register following thereto. The error data are periodically appended to the digital signals, which are in turn reproduced under a stable receiving state insusceptible of errors in order to quantitatively evaluate the extraneous sound suppressing effect of the receiving circuit.

Abstract: A signal processing apparatus includes a first signal processor which processes a first channel of signal; and a second signal processor which processes a second channel of signal independently from the processing by the first signal processor.

Abstract: The present invention relates to the control of a phase control circuit and, more particularly, to a DPLL circuit used to accomplish synchronization when connecting a digital network connecting unit such as a digital service unit (DSU) with a radio unit such as a personal handy phone system (PHS); it prevents a problem involved in the phase control during sending or receiving. The phase control circuit has: a phase comparator circuit that compares the phase difference between a synchronizing signal and a signal to be controlled and outputs a phase control signal according to a comparison result; a phase changing circuit that changes the phase of the signal to be controlled according to the phase control signal; and a mask circuit that masks the phase control signal supplied to the phase changing circuit according to a phase control disable signal.

Abstract: A timing control circuit includes a synchronous detecting portion which detects a synchronous pattern data of a received signal which has been demodulated based on a first control signal and generates a detection result, a first counter portion which generates a first signal at each first cycle based on the detection result, a second counter portion which generates a second signal at each second cycle based on the detection result, and a first control portion which generates the first control signal based on the first and second signals.

Abstract: An apparatus for decoding encoded voice data comprises a demodulator (101) which demodulates the encoded voice data (RF) and provides a demodulated encoded voice data (APO, RD), an adaptive differential pulse code modulation decoder (102) which decodes the demodulated encoded voice data and provides a pulse code modulation data (PO), an error detector (103) which detects whether error is present in the encoded voice data based on the demodulated encoded voice data and outputs a detection result (CRCERR) and a limiter (104) which outputs either the pulse code modulation data (POL) or a limit data (POL) in accordance with the detection result (CRCERR).

Abstract: An output circuit having a function of two or more external interfaces is disclosed. The disclosed output circuit has an input circuit generating an internal input signal in response to an external input signal, an output circuit including a pMOS transistor coupled between a positive potential source and an output terminal and an nMOS transistor coupled between a reference potential source and the output terminal. A gate of one of the transistors receives the internal input signal. The disclosed output circuit further has a control circuit receiving the internal input signal and the control signal and outputting an internal signal in response to the internal input signal and the control signal to a gate of the other one of the transistor. The control circuit outputs the internal input signal as the internal signal where the control signal has a first level.

Abstract: Disclosed herein is a receiving circuit comprising demodulator 101 which pulls in the phase of each of burst signals respectively having preambles 701 and 711 each storing phase information or data therein, synchronous pattern parts 702 and 712 each storing synchronous information therein, and data parts 703 and 713 each storing the data therein, and outputs data obtained by demodulating the burst signal, a controller 110 which performs counting based on the demodulated data to output a timing signal, and a storage unit 102 which stores or outputs the demodulated data, based on the timing signal.

Abstract: An output circuit having a function of two or more external interfaces is disclosed. The disclosed output circuit has an input circuit generating an internal input signal in response to an external input signal, an output circuit including a pMOS transistor coupled between a positive potential source and an output terminal and an nMOS transistor coupled between a reference potential source and the output terminal. A gate of one of the transistors receives the internal input signal. The disclosed output circuit further has a control circuit receiving the internal input signal and the control signal and outputting an internal signal in response to the internal input signal and the control signal to a gate of the other one of the transistor. The control circuit outputs the internal input signal as the internal signal where the control signal has a first level.

Abstract: An output circuit having a function of two or more external interfaces is disclosed. The disclosed output circuit has an input circuit generating an internal input signal in response to an external input signal, an output circuit including a pMOS transistor coupled between a positive potential source and an output terminal and an nMOS transistor coupled between a reference potential source and the output terminal. A gate of one of the transistors receives the internal input signal. The disclosed output circuit further has a control circuit receiving the internal input signal and the control signal and outputting an internal signal in response to the internal input signal and the control signal to a gate of the other one of the transistor. The control circuit outputs the internal input signal as the internal signal where the control signal has a first level.

Abstract: A voltage-controled oscillator circuit generates an output signal with a frequency that varies in response to a control current regulated by an applied control voltage. The voltage-controlled oscillator also thresholds the control voltage according to two different threshold voltages, producing a thresholded signal with a hysteresis characteristic. The thresholded signal switches a constant-current circuit on and off. When switched on, the constant-current adds a fixed current to the control current, thus widening the frequency range of the output signal.