Abstract: A plurality of resistors are series-connected between a first terminal to which a power source potential is applied and a second terminal to which a ground potential is applied. The plurality of resistors have such plane patterns that the current conduction paths thereof are arranged in parallel to one another. Switches of a first group for changing a connection between the plurality of resistors and an output terminal are respectively connected between the plurality of resistors and the output terminal. Switches of a second group for changing a connection between the plurality of resistors and the second terminal are respectively connected between the plurality of resistors and the second terminal. The conduction states of the switches of the first group are controlled by an output signal of a first control circuit and the conduction states of the switches of the second group are controlled by an output signal of a second control circuit.

Abstract: A NAND-system address decoder is configured by arranging the P-channel- and N-channel logical blocks in parallel and input wires to which address signals are supplied is extendedy formed in the direction in which the above logical blocks are arranged. And, output lines extended from each logical block are connected to a output portion in parallel. The P-channel- and N-channel logical circuits are configured by collection of local decode circuits. The local decode circuit is composed of a P-channel MISFET circuit consisting of parallely-connected P-channel MISFETs corresponding to the number of address-signal bits and a N-channel MISFET circuit consisting of serially-connected N-channel MISFETs corresponding to the number of address-signal bits. The MISFET configuring each MISFET circuits are configured so that a gate will be set at the position to which the above input wires will extend.

Abstract: A plurality of resistors are connected between a source terminal to which a reference voltage is applied and a grounded terminal. A plurality of switches, which constitute a first switch group and derives voltages divided by the resistors, are respectively connected to the odd-numbered connection nodes among the connection nodes between the grounded terminal and a resistor and between each adjacent resistors. A plurality of switches, which constitute a second switch group and derives voltages divided by the resistors, are respectively connected to the even-numbered connection nodes among the connection nodes between the grounded terminal and a resistor and between each adjacent resistors. Each of the switches of the first and second switch groups is connected to a logical circuit serving as a decoder for selecting one of the switches in accordance with the content of bits other than the least significant bit of an input digital signal.