Patents by Inventor Kiyohito Ito

Kiyohito Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11728176
    Abstract: A treatment method is provided that includes an embedding step of embedding an organic film in an undercoat film in which a depression is formed; and an etching step of performing etching, after the embedding step, until at least a portion of a top of the undercoat film is exposed.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: August 15, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Kiyohito Ito, Shinya Morikita, Kensuke Taniguchi, Michiko Nakaya, Masanobu Honda
  • Patent number: 11380545
    Abstract: There is provision of a processing method including a) depositing deposits on a patterned mask layer formed over an etching film; b) removing a part of the mask layer, a part of the deposits, or both the part of the mask layer and the part of the deposits; and c) repeating a) and b) at least once, thereby causing a taper angle of a side surface of a pattern formed in the mask layer to be a desired angle.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: July 5, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Shota Yoshimura, Kiyohito Ito
  • Publication number: 20210313187
    Abstract: A treatment method is provided that includes an embedding step of embedding an organic film in an undercoat film in which a depression is formed; and an etching step of performing etching, after the embedding step, until at least a portion of a top of the undercoat film is exposed.
    Type: Application
    Filed: August 8, 2019
    Publication date: October 7, 2021
    Inventors: Kiyohito ITO, Shinya MORIKITA, Kensuke TANIGUCHI, Michiko NAKAYA, Masanobu HONDA
  • Patent number: 10950458
    Abstract: An etching method is provided. The etching method is performed on a substrate having a first film to a third film. The third film is provided on an underlying region, the second film is provided on the third film, the first film is provided on the second film. The second film contains silicon and nitrogen. The first film to the third film are etched in sequence. Plasma of a processing gas containing fluorine and hydrogen is used in the etching of the first film to the third film. A temperature of the substrate is set to be equal to or less than 20° C. at least in the etching of the second film.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 16, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yasutaka Hama, Shinya Morikita, Kiyohito Ito
  • Patent number: 10886138
    Abstract: An etching shape can be suppressed from having non-uniform pattern. A substrate processing method includes burying an organic film in a recess surrounded by a silicon-containing film formed on a sidewall of a pattern of photoresist on a target film; and etching or sputtering the organic film and the silicon-containing film under a condition in which a selectivity thereof is about 1:1.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: January 5, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Timothy Tianshyun Yang, Shinya Morikita, Kiyohito Ito, Michiko Nakaya, Masanobu Honda
  • Publication number: 20200144051
    Abstract: There is provision of a processing method including a) depositing deposits on a patterned mask layer formed over an etching film; b) removing a part of the mask layer, a part of the deposits, or both the part of the mask layer and the part of the deposits; and c) repeating a) and b) at least once, thereby causing a taper angle of a side surface of a pattern formed in the mask layer to be a desired angle.
    Type: Application
    Filed: November 1, 2019
    Publication date: May 7, 2020
    Inventors: Shota YOSHIMURA, Kiyohito ITO
  • Publication number: 20190355588
    Abstract: An etching shape can be suppressed from having non-uniform pattern. A substrate processing method includes burying an organic film in a recess surrounded by a silicon-containing film formed on a sidewall of a pattern of photoresist on a target film; and etching or sputtering the organic film and the silicon-containing film under a condition in which a selectivity thereof is about 1:1.
    Type: Application
    Filed: May 20, 2019
    Publication date: November 21, 2019
    Inventors: Timothy Tianshyun Yang, Shinya Morikita, Kiyohito Ito, Michiko Nakaya, Masanobu Honda
  • Publication number: 20190214269
    Abstract: An etching method is provided. The etching method is performed on a substrate having a first film to a third film. The third film is provided on an underlying region, the second film is provided on the third film, the first film is provided on the second film. The second film contains silicon and nitrogen. The first film to the third film are etched in sequence. Plasma of a processing gas containing fluorine and hydrogen is used in the etching of the first film to the third film. A temperature of the substrate is set to be equal to or less than 20° C. at least in the etching of the second film.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 11, 2019
    Inventors: Yasutaka Hama, Shinya Morikita, Kiyohito Ito
  • Patent number: 9576812
    Abstract: Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: February 21, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Elliott Franke, Vinayak Rastogi, Akiteru Ko, Kiyohito Ito
  • Publication number: 20160293435
    Abstract: Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 6, 2016
    Inventors: Elliott Franke, Vinayak Rastogi, Akiteru Ko, Kiyohito Ito
  • Patent number: 9443731
    Abstract: Provided is a method for increasing pattern density on a substrate comprising a structure with a patterned layer with a first composition and a sidewall and a cap layer of a second composition formed atop said structure. The sidewall is exposed to a chemical environment and creates a chemically modified sidewall layer of a third composition. The cap layer and an interior, non-modified portion of said structure is removed using an etching process to leave behind said chemically modified sidewall layer. A pattern transfer etch of said sidewall chemically modified layer onto the underlying layer of said substrate is performed. One or more integration operating variables are controlled to achieve target critical dimensions comprising width, height, sidewall angle, line width roughness, and/or line edge roughness of said structure.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: September 13, 2016
    Assignee: Tokyo Electron Limited
    Inventors: David L. O'Meara, Angelique D. Raley, Akiteru Ko, Kiyohito Ito
  • Publication number: 20160247680
    Abstract: Provided is a method for increasing pattern density on a substrate comprising a structure with a patterned layer with a first composition and a sidewall and a cap layer of a second composition formed atop said structure. The sidewall is exposed to a chemical environment and creates a chemically modified sidewall layer of a third composition. The cap layer and an interior, non-modified portion of said structure is removed using an etching process to leave behind said chemically modified sidewall layer. A pattern transfer etch of said sidewall chemically modified layer onto the underlying layer of said substrate is performed. One or more integration operating variables are controlled to achieve target critical dimensions comprising width, height, sidewall angle, line width roughness, and/or line edge roughness of said structure.
    Type: Application
    Filed: February 20, 2015
    Publication date: August 25, 2016
    Inventors: David L. O'Meara, Angelique D. Raley, Akiteru Ko, Kiyohito Ito
  • Patent number: 9257280
    Abstract: A method which is particularly advantageous for improving a Self-Aligned Pattern (SAP) etching process. In such a process, facets formed on a spacer layer can cause undesirable lateral etching in an underlying layer beneath the spacer layer when the underlying layer is to be etched. This detracts from the desired vertical form of the etch. The etching of the underlying layer is performed in at least two steps, with a passivation layer or protective layer formed between the etch steps, so that sidewalls of the underlying layer that was partially etched during the initial etching are protected. After the protective layer is formed, the etching of the remaining portions of the underlying layer can resume.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: February 9, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akiteru Ko, Angelique D. Raley, Kiyohito Ito
  • Publication number: 20140357084
    Abstract: A method which is particularly advantageous for improving a Self-Aligned Pattern (SAP) etching process. In such a process, facets formed on a spacer layer can cause undesirable lateral etching in an underlying layer beneath the spacer layer when the underlying layer is to be etched. This detracts from the desired vertical form of the etch. The etching of the underlying layer is performed in at least two steps, with a passivation layer or protective layer formed between the etch steps, so that sidewalls of the underlying layer that was partially etched during the initial etching are protected. After the protective layer is formed, the etching of the remaining portions of the underlying layer can resume.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 4, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akiteru KO, Angelique D. Raley, Kiyohito Ito
  • Publication number: 20140284308
    Abstract: There are provided a plasma etching method and a plasma etching apparatus, capable of suppressing occurrence of local bias in etching rate and suppressing occurrence of charge-up damage. The plasma etching method of etching a silicon layer of a substrate to be processed using the plasma etching apparatus sets the pressure in a processing chamber to 13.3 Pa or more and applies, to a lower electrode, a first high-frequency power with a first frequency and a second high-frequency power with a second frequency that is lower than the first frequency and is a frequency of 1 MHz or lower.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 25, 2014
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOKYO ELECTRON LIMITED
    Inventors: Shoichiro MATSUYAMA, Akitaka SHIMIZU, Susumu NOGAMI, Kiyohito ITO, Tokuhisa OHIWA, Katsunori YAHASHI
  • Patent number: 8232207
    Abstract: In a substrate processing method of processing a substrate that includes an oxide layer as a mask layer and a silicon layer as a target layer to be processed, the silicon layer is etched while depositing a deposit on a surface of the oxide layer by a plasma generated from a mixed gas of a fluorine-based gas, a bromine-based gas, O2 gas, and SiCl4 gas to secure a thickness of the mask layer.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: July 31, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Kosuke Ogasawara, Kiyohito Ito
  • Publication number: 20100167549
    Abstract: In a substrate processing method of processing a substrate that includes an oxide layer as a mask layer and a silicon layer as a target layer to be processed, the silicon layer is etched while depositing a deposit on a surface of the oxide layer by a plasma generated from a mixed gas of a fluorine-based gas, a bromine-based gas, O2 gas, and SiCl4 gas to secure a thickness of the mask layer.
    Type: Application
    Filed: December 24, 2009
    Publication date: July 1, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kosuke OGASAWARA, Kiyohito Ito
  • Publication number: 20040222190
    Abstract: In a plasma processing method, a silicon layer of an object to be processed is etched by using a plasma of a processing gas introduced into an airtight processing chamber through a patterned mask. The processing gas contains a gaseous mixture of HBr, O2 and SiF4 and, additionally, one or both of SF6 gas and NF3 gas; and a gas containing C and F is further added to the processing gas.
    Type: Application
    Filed: March 31, 2004
    Publication date: November 11, 2004
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Katsumi Horiguchi, Kenji Yamamoto, Kiyohito Ito, Keiichi Kanno