Abstract: A memory device according to one embodiment includes a resistance change film, an insulating film provided on the resistance change film, a first wiring provided on the insulating film and being not in contact with the resistance change film, and a high resistance film having a higher resistivity than the first wiring. The high resistance film is provided on a side surface of a stacked body including the insulating film and the first wiring, and the high resistance film is electrically connected between the first wiring and the resistance change film.

Abstract: A memory device according to one embodiment includes a resistance change film, an insulating film provided on the resistance change film, a first wiring provided on the insulating film and being not in contact with the resistance change film, and a high resistance film having a higher resistivity than the first wiring. The high resistance film is provided on a side surface of a stacked body including the insulating film and the first wiring, and the high resistance film is electrically connected between the first wiring and the resistance change film.

Abstract: A memory device includes a substrate, first and second wirings above the substrate, a third wiring above the first and second wirings, a fourth wiring above the third wiring, a first contact electrically connected between the first wiring and the fourth wiring, a first insulator on the first contact, and a second contact on the first insulator, the second contact being electrically connected between the second wiring and the third wiring. The first contact overlaps the second contact in a direction that is orthogonal to an upper surface of the substrate.

Abstract: A memory device includes a substrate, first and second wirings above the substrate, a third wiring above the first and second wirings, a fourth wiring above the third wiring, a first contact electrically connected between the first wiring and the fourth wiring, a first insulator on the first contact, and a second contact on the first insulator, the second contact being electrically connected between the second wiring and the third wiring. The first contact overlaps the second contact in a direction that is orthogonal to an upper surface of the substrate.

Abstract: According to one embodiment, a memory device includes a substrate, a first wiring layer including a first interconnect extending in a first direction which is disposed on the substrate, a second wiring layer including a second interconnect which is disposed so as to extend in a second direction intersecting the first direction above the first wiring layer, a memory cell which is disposed between the first interconnect and the second interconnect, and a pattern which is spaced from the memory cell. The memory cell and the pattern, respectively, includes a resistance change layer which is disposed between the first wiring layer and the second wiring layer, and an electrode layer which is provided below the second wiring layer and directly above the resistance change layer, and the memory cell further including a metal source layer which is provided between the resistance change layer and the electrode layer.

Abstract: According to one embodiment, a memory device includes a first wiring line extending in a first direction, a second wiring line extending in a first direction, the first wiring line and the second wiring line being separated from each other, a third wiring line separated from the first wiring line and the second wiring line, at least one portion of the third wiring line extending in a second direction crossing the first direction, a fourth wiring line separated from the first wiring line and the second wiring line, at least one portion of the fourth wiring line extending in the second direction, a first interconnect connected between a side surface of the first wiring line and a side surface of the third wiring line, and a second interconnect connected between a side surface of the second wiring line and a side surface of fourth wiring line.

Abstract: A memory device according to an embodiment, includes a conductive member, a first interconnect, a second interconnect, a first memory element, a first connecting member, a first via and a first contact. The first interconnect is provided on the conductive member. The first interconnect extends in a first direction. The second interconnect is provided on the conductive member above or below the first interconnect. The second interconnect extends in a second direction crossing the first direction. The first memory element is connected between the first interconnect and the second interconnect. The first connecting member is made of the same material as the first interconnect. The first connecting member is separated from the first interconnect. The first via connects the second interconnect to the first connecting member. The first contact connects the first connecting member to the conductive member.

Abstract: A memory device according to one embodiment includes a resistance change film, an insulating film provided on the resistance change film, a first wiring provided on the insulating film and being not in contact with the resistance change film, and a high resistance film having a higher resistivity than the first wiring. The high resistance film is provided on a side surface of a stacked body including the insulating film and the first wiring, and the high resistance film is electrically connected between the first wiring and the resistance change film.

Abstract: A memory device according to one embodiment includes a substrate, a first wiring placed on the substrate and extending in a first direction, a second wiring placed on the first wiring and extending in a second direction, a memory element coupled the first wiring and the second wiring, an engagement member coupled a portion of the second wiring, the portion is displaced from a region directly above the first wiring, a via engaged with the engagement member, a stopper member placed in a region including a region directly below the engagement member, and an interlayer insulating film provided on the substrate and covering the first wiring, the second wiring, the memory element, the engagement member, the via, and the stopper member.

Abstract: According to an embodiment, a nonvolatile memory device includes: a first interconnection layer extending in a first direction; a second interconnection layer extending in a second direction crossing the first direction, the second interconnection layer including a metal-containing layer and a metal ion source layer, and the metal ion source layer being provided on the first interconnection layer side; and a resistance change layer provided in a position where the first interconnection layer and the second interconnection layer cross each other and a metal ion released from the metal ion source layer being capable to be diffused into the resistance change layer. At least part of the second interconnection layer protrudes to the first interconnection layer side in a cross section of the second interconnection layer cut perpendicularly to the second direction.

Abstract: A memory device according to an embodiment, includes a substrate, two or more resistance change memory cells stacked on the substrate, two or more transistors stacked on the substrate, and two or more wirings stacked on the substrate. One of the memory cells and one of the transistors are connected to each other via one of the wirings.

Abstract: A nonvolatile memory device according to an embodiment includes: a semiconductor substrate; a memory cell array unit provided on an upper side of the semiconductor substrate; an integrated circuit unit provided between the memory cell array unit and the semiconductor substrate; and a peripheral circuit unit provided on the semiconductor substrate. The integrated circuit unit includes: a first contact electrode electrically connected to one of plurality of first interconnection layers; a second contact electrode connected to the peripheral circuit unit; and a first switching element connected between the first contact electrode and the second contact electrode, and conduction between the first contact electrode and the second contact electrode being controlled by a control circuit unit provided in the peripheral circuit unit.

Abstract: According to an embodiment, a nonvolatile memory device includes: a first interconnection layer extending in a first direction; a second interconnection layer extending in a second direction crossing the first direction, the second interconnection layer including a metal-containing layer and a metal ion source layer, and the metal ion source layer being provided on the first interconnection layer side; and a resistance change layer provided in a position where the first interconnection layer and the second interconnection layer cross each other and a metal ion released from the metal ion source layer being capable to be diffused into the resistance change layer. At least part of the second interconnection layer protrudes to the first interconnection layer side in a cross section of the second interconnection layer cut perpendicularly to the second direction.

Abstract: According to one embodiment, a memory device includes a plurality of first interconnects extending in a first direction, and having divided portions formed respectively in the first interconnects at mutually-different positions in the first direction, a plurality of semiconductor members, each of the semiconductor members being disposed to extend over the first interconnects, a first insulating film disposed to cause each of the semiconductor members to be respectively connected to each of the first interconnects between portions of the first interconnects on two sides of the divided portions and to cause each of the semiconductor members to be insulated from other one of the first interconnects, a second insulating film provided on the semiconductor members, an electrode provided on the second insulating film, a memory cell member provided on the first interconnects, and a second interconnect provided on the memory cell member.

Abstract: According to one embodiment, a memory device includes a first interconnect having a divided portion formed in the first interconnect, a memory cell member provided on the first interconnect, a second interconnect provided on the memory cell member, a semiconductor member provided on the first interconnect to be connected between portions of the first interconnect on two sides of the divided portion, an insulating film covering an upper surface of the semiconductor member and a side surface of at least an upper portion of the semiconductor member, and an electrode provided on the insulating film to cover the upper surface of the semiconductor member and the side surface of the at least an upper portion of the semiconductor member with the insulating film interposed.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device, includes: control gate electrodes provided above semiconductor regions; a charge accumulation layer; a first insulating film; a second insulating film; a select gate electrode; a conductive structural body located on opposite side of the select gate electrode from the plurality of control gate electrodes, the conductive structural body provided on each of the plurality of semiconductor regions, and the conductive structural body including a fourth insulating film, a semiconductor-containing layer provided on the fourth insulating film, and a conductive film in contact with a sidewall of the fourth insulating film and a sidewall of the semiconductor-containing layer; and a contact electrode extending in a third direction from a side of the plurality of semiconductor regions to a side of the plurality of control gate electrodes, and the contact electrode connected to the conductive structural body.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of element-separating insulators, and contacts. The plurality of element-separating insulators partition the upper layer portion into a plurality of active areas extending in a first direction. The contacts are connected to the active areas. A recess is made in a part in the first direction of an upper surface of each of the active areas. The recess is made across the entire active area in a second direction orthogonal to the first direction. Positions in the first direction of two of the contacts connected respectively to mutually-adjacent active areas are different from each other. One of the contacts is in contact with a side surface of the recess and not in contact with a bottom surface of the recess.

Abstract: A nonvolatile memory according to an embodiment includes a first wiring line; a second wiring line arranged above the first wiring line and extending in a direction crossing the first wiring line; and a resistance change layer arranged in an intersection region of the first wiring line the second wiring line, the second wiring line including a first member extending in the direction in which the second wiring line extends, and an electrode layer containing a metal element arranged on a side surface of the first member along the direction in which the second wiring line extends, a lower surface of the electrode layer being in contact with an upper surface of the resistance change layer.

Abstract: A memory device according to an embodiment, includes a substrate, two or more resistance change memory cells stacked on the substrate, two or more transistors stacked on the substrate, and two or more wirings stacked on the substrate. One of the memory cells and one of the transistors are connected to each other via one of the wirings.

Abstract: According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.