Abstract: A data processing apparatus, including a number of electronic circuit units, in which high-speed data can be transmitted among the electronic circuit units. When data is transmitted from one electronic circuit unit to another electronic circuit unit, a clock signal to fetch the data in the sink side electronic circuit unit is transmitted from the source side electronic circuit unit via a clock signal line having the same signal propagation delay characteristics as those of the data signal line.

Abstract: A method for wiring a power supply for a large-scale integrated circuit. The power supply wires define a power supply grid surrounding lattice openings with fixed longitudinal and transverse lattice dimensions. The wire width is determined based on the integrated circuit chip size, the number of function circuits to be on the integrated circuit, the electrical power requirements of the function circuits, and the fixed longitudinal and transverse lattice dimensions. Longitudinal and transverse locations of the power supply wires chips are determined based on the determined wire width and the fixed longitudinal and transverse dimensions of the lattice openings. Alternatively, the wire width may be fixed and the dimensions of the lattice openings determined based on the integrated circuit chip size, the number of function circuits, the electrical power requirements of the function circuits and that wire width.

Abstract: The invention prepares test data on a logic LSI which includes a plurality of signal pins, a control pin for inputting an external control signal, and control circuitry responsive to the external control signal for setting the signal pins in a desired state according to a specified function thereof.In accordance with the invention, the method comprises the steps of storing first data in a first memory, the first data being representative of a specified function of individual pins; storing the second data in a second memory, the second data representing a plurality of pin states corresponding to a plurality of signal states set by the external control signal; reading first and second data from the first and second memory; selectively communicating the test control signal to the integrated circuit, generating third data representative of each pin state of individual pins of each signal state set by the external control signal; and storing the third data into a file as test data.