Abstract: A delay circuit is provided with an npn type of transistor of which a base is connected to an input terminal, a first constant current source through which a constant current flows from an emitter of the transistor to ground, a first capacitor arranged between the emitter of the transistor and an electric source terminal, a second capacitor C.sub.22 arranged between a collector of the transistor and an output terminal, a first resistor arranged between the emitter of the transistor and the output terminal, a second resistor arranged between the collector of the transistor and the electric source terminal. The constant current of the constant current source is changeable, and an emitter resistance of the transistor is changed depending on the constant current. Therefore, an analog signal applied to the input terminal is changeably delayed by coaction of the resistors, the capacitors and the emitter resistance adjusted by changing the constant current of the constant current source.

Abstract: A semiconductor integrated circuit device includes a plurality of digit lines, a plurality of memory cells, a sense amplifier circuit, a plurality of digit line biasing circuits, and a bias voltage generating circuit. Non-selected digit lines are biased to a predetermined voltage by the bias voltage generating circuit and the digit line bias circuits during the read-out mode, which results in the advantage that the speed in which the selected digit line is charged to the equilibrium values is high, hence the operation speed of the circuit is high. The present invention may be effectively embodied in such an EEPROM which is large in capacity or scale and which requires a high speed operation.

Abstract: An electrically erasable and programmable read only memory device has a sense amplifier circuit for changing an output voltage level at the output node thereof indicative of either an erased or a write-in state of a memory cell to be accessed, and the output voltage level is compared with a reference voltage level so as to see whether the output voltage is indicative of the erased state or the write-in state, wherein the sense amplifier circuit is associated with a current make-up circuit for compensating the current to the output node of the sense amplifier circuit so that the output voltage level rapidly reaches a high or low voltage level regardless of fluctuation of the reference voltage level.

Abstract: A photographic material comprising a silver halide photographic material which has a magnetic recording layer having a coercive force of at least 400 Oe and a patrone for silver halide photographic material wherein a leading end of a silver halide photographic material wound around a spool is delivered from a film leading-out port of a main body of the patrone to the outside by rotating said spool in the direction of film delivery, said spool being rotatably provided in the main body of the patrone.

Abstract: A nonvolatile semiconductor memory device for use as a flash EEPROM includes a plurality of sectors each comprising a plurality of main memory cell regions each composed of a matrix of nonvolatile memory cells and at least one redundant memory cell region composed of a matrix of nonvolatile memory cells. When one of said nonvolatile memory cells in any one of the sectors is found defective and is selected by addressing, it is replaced with one of the nonvolatile memory cells in the redundant memory cell region.

Abstract: An electrically erasable and programmable read only memory device has a sense amplifier circuit for changing an output voltage level at the output node thereof indicative of either an erased or a write-in state of a memory cell to be accessed, and the output voltage level is compared with a reference voltage level so as to see whether the output voltage is indicative of the erased state or the write-in state, wherein the sense amplifier circuit is associated with a current make-up circuit for compensating the current to the output node of the sense amplifier circuit so that the output voltage level rapidly reaches a high or low voltage level regardless of fluctuation of the reference voltage level.

Abstract: A tracking error detecting circuit in which tracking error detecting pilot signals having different frequencies are added to a main signal every track and recorded onto a magnetic recording medium, and upon reproduction, reproduction output levels of the pilot signals reproduced as crosstalks from both of adjacent tracks are compared, and a tracking error is detected. n signals having the same frequencies as those of the pilot signals and whose phases are different are generated and multiplied to the reproduction signal. Unnecessary components are eliminated by n LPFs (Lowpass filters). The amplitude values of the reproduced pilot signals are vector separated and detected. Further, the vector separated amplitude values are vector synthesized and detected. Therefore, by multiplying the signals having the same frequencies as those of the pilot signals, the synchronous detection is performed.

Abstract: A read only memory device comprises a memory cell array, a selector unit interconnecting one of the memory cells to an input node of a sense amplifier unit for producing a read-out signal at a read-out node, a reference unit for producing a reference signal with an intermediate voltage level between voltage levels corresponding to logic "1" bit and logic "0" bit, and a voltage comparator coupled to the sense amplifier unit and the reference unit, wherein the sense amplifier unit has a load transistor continuously supplying current to the read-out node, a transfer gate transistor for interconnecting the input node and the read-out node under the control of an inverting amplifier coupled to the input node, and a charging transistor for providing an auxiliary current path to the read-out node upon rapid decay in voltage level at the read-out node, thereby causing the read-out signal to quickly become stable.

Abstract: In a flash type EEPROM comprising a memory cell matrix, an X decoder and a Y decoder, the X decoder includes a first circuit for charging an output of the first circuit to a voltage supply voltage when the first circuit is selected by an address signal, a depletion N-channel MOS transistor connected between the output node of the first circuit and a corresponding word line and having a gate connected to receive a control voltage, a second circuit for generating a high voltage at an output node of the second circuit at the time of a write mode, and a enhancement P-channel MOS transistor connected between the output node of the second circuit and the corresponding word line and having a gate connected to receive an erase verify signal. In an erase voltage verify mode, the gate of the depletion N-channel transistor is brought to a low level and the enhancement P-channel MOS transistor is turned off, so that a selected word lines is charged through the depletion N-channel MOS transistor.

Abstract: A circuit for detecting a power supply voltage in a memory apparatus comprises a first circuit, through which flows a first saturating current which is constant when a power supply voltage is above a predetermined value, and a second circuit, through which flows a second current which increases in proportion to the power supply voltage when it is above the predetermined value. The first circuit includes an N-channel enhancement mode insulated gate field effect transistor ("NE-IGFET"), and the second circuit includes an N-channel depletion mode insulated gate field effect transistor ("ND-IGFET"). A power supply voltage is thus detected by responsive to a difference between the threshold values of the NE-IFGET and ND-IFGET, which is not dependent on a temperature.

Abstract: A power supply voltage drop detection circuit has first and second N-channel field-effect-transistors. The drain of the first N-channel FET is connected to a power supply voltage line and its gate to ground. The drain of the second N-channel FET connected to the source of the first N-channel FET and its source is connected to the ground. A control voltage to the gate of the second N-channel FET maintains the second N-channel FET conducting. A P-channel field-effect-transistor has its source connected to the power supply voltage line and its gate connected to a connection node between the first and second N-channel field-effect-transistors. A third N-channel FET has its drain connected to the drain of the P-channel FET and its source connected to the ground. The gate of the third N-channel FET receives a controlled gate voltage which maintains the third N-channel FET conducting. An inverter has its input connected to a node between the P-channel FET and the third N-channel FET.

Abstract: In a semiconductor memory device, an output of a sense amplifier circuit and a reference voltage of a reference voltage producing circuit are compared to decide whether a content of a selected memory cell is "1" or "0". A load characteristic of a load circuit of the reference voltage producing circuit is different from that of the sense amplifier circuit, so that current flowing through a reference field effect transistor can be increased to a level of current flowing through a memory cell in which "O" is stored. Therefore, a time in which an output voltage of the reference voltage producing circuit is lowered from a voltage set at the stand-by mode to the reference voltage set at the reading mode is shortened at the reading mode subsequent to the stand-by mode.

Abstract: There is disclosed a non-volatile semiconductor memory device provided with column latching circuits each temporally memorizing plural bytes of input data bits, and gate and drain voltage levels of each of memory cell transistors are controlled on the basis of the input data bits latched into the column latching circuits for a simultaneous write-in operation, so that only column address selecting lines and row address lines are provided for specifying a plurality of memory cell groups in the simultaneous write-in operation.

Abstract: For sufficient diagnostic operation, there is disclosed a semiconductor memory device having a write-in mode, a read-out mode and a diagnostic mode.

Abstract: A semiconductor memory system of, typically, the EEPROM type comprising a memory cell including a memory transistor which is typically a SAMOS type non-volatile device having a first threshold voltage higher than a predetermined reference level when the memory transistor is in a state storing a logic "0" bit of data and a second threshold voltage lower than the reference level when the memory transistor is in a state storing the other of the logic "1" bit of data. A control circuit for controlling the control gate of the SAMOS type memory transistor, comprising a combination of transistors arranged to be operative to produce a readout voltage intervening between the reference level and the first threshold voltage, the memory transistor being responsive to the readout voltage for having a first state if the memory transistor has the first threshold voltage and a second state if the memory transistor has the second threshold voltage.

Abstract: A semiconductor memory device is disclosed in which an output data voltage of a sense amplifier is compared with a reference voltage to produce an output data corresponding to the data stored in the selected memory cell. The reference voltage is generated in response to a current flowing through a dummy memory transistor having the same device structure as a memory transistor and is thus variable if the current flowing through the memory transistor is deviated from the designed value.

Abstract: A non-linear signal processing apparatus used in a video tape recorder or a video disk player is disclosed. The time variation of an input signal or a processed version thereof is non-linearly processed by a differential circuit and a closed loop including a non-linear circuit. The non-linearly processed time variation of the signal or a processed version thereof is arithmetically combined with the input signal. Thus, the same non-linear characteristic as that obtained by the prior art analog signal technique is attained by the digital signal processing technique, which is superior in integrity and stability. By appropriately selecting the characteristic of the non-linear circuit, better results than those obtainable by the analog signal processing technique are achieved.

Abstract: In a chrominance signal processing apparatus for processing a sampled and digitized signal, when a first carrier chrominance signal is frequency-converted to a second carrier chrominance signal whose carrier angular frequency is a second reference angular frequency by use of a frequency converting signal, the present invention provides an arrangement such that: a variation component of a carrier signal frequency from a first reference angular frequency signal which the first carrier chrominance signal has, namely, an angular frequency difference signal is derived by an APC circuit from the first and second reference angular frequency signals, angular frequency difference signal, and further various kinds of angular frequency signals and phase signals which give necessary functions and performances as a chrominance signal processing circuit are added or subtracted in the states of the angular frequency signals and phase signals thereby simplifying the process for obtaining the above frequency converting signal

Abstract: A voltage detection circuit for detecting an input voltage larger in absolute value than a power supply voltage is disclosed. This circuit comprises a first transistor connected between a terminal supplied with the input voltage and a circuit node, and a second and a third complementary transistors connected in series between the circuit node and a reference potential terminal. The first transistor is used as a voltage-dropping means, and the gates of the second and third transistors are commonly supplied with the power supply voltage. When the potential difference between the circuit node and the gate of the second transistor exceeds the threshold value of the same transistor, the second transistor is turned ON and the potential at the connection point of the second and third transistors begins to change. At this time, the input voltage is higher in absolute value than the power supply voltage because the first transistor operates as the voltage-dropping means.

Abstract: A dropout compensation system used with a video tape recorder, video disc, etc. is disclosed. In conventional modulation systems, a reproduced signal which has been modulated in a modulation system in which the signal information is determined by the zero passage of the carrier, is delayed in the form of the modulated signal, and if a dropout occurs, the reproduced signal is switched to the delayed signal by a first switch thereby to compensate for the dropout. The phase of the modulated signal becomes discontinuous each time the switch is operated, thus causing an offensive spark-like interference upon demodulation. The invention is intended for reducing these noises and comprises a second demodulator for normally demodulating the delayed signal and a second switch operated at a different timing from the first switch in response to the dropout.