Patents by Inventor Kiyokazu Ishige
Kiyokazu Ishige has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8675385Abstract: A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.Type: GrantFiled: June 24, 2011Date of Patent: March 18, 2014Assignee: Renesas Electronics CorporationInventors: Hiromichi Takaoka, Kenichi Hidaka, Hiroshi Tsuda, Kiyokazu Ishige, Yoshitaka Kubota, Takuji Onuma
-
Patent number: 8530949Abstract: An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact.Type: GrantFiled: September 30, 2011Date of Patent: September 10, 2013Assignee: Renesas Electronics CorporationInventors: Takuji Onuma, Kenichi Hidaka, Hiromichi Takaoka, Yoshitaka Kubota, Hiroshi Tsuda, Kiyokazu Ishige
-
Publication number: 20120080736Abstract: An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact.Type: ApplicationFiled: September 30, 2011Publication date: April 5, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takuji ONUMA, Kenichi HIDAKA, Hiromichi TAKAOKA, Yoshitaka KUBOTA, Hiroshi TSUDA, Kiyokazu ISHIGE
-
Publication number: 20120044741Abstract: A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.Type: ApplicationFiled: June 24, 2011Publication date: February 23, 2012Applicant: Renesas Electronics CorporationInventors: Hiromichi Takaoka, Kenichi Hidaka, Hiroshi Tsuda, Kiyokazu Ishige, Yoshitaka Kubota, Takuji Onuma
-
Patent number: 6979856Abstract: A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor substrate between the second diffusion region and a third diffusion region, and a second gate electrode provided on the second insulating film. The first and second diffusion regions, first insulating film, and first gate electrode constitute a first memory cell, while the second and third diffusion regions, second insulating film, and second gate electrode constitute a second memory cell. The first and second gate electrodes are connected in common to form a word line electrode. The first and third diffusion regions are connected to first and second read bit lines. The second diffusion region is connected to a program and erase bit line.Type: GrantFiled: August 27, 2003Date of Patent: December 27, 2005Assignee: NEC Electronics CorporationInventors: Teiichiro Nishizaka, Isami Sakai, Akira Yoshino, Shinichi Kawai, Kiyokazu Ishige, Tomohiro Hamajima, Motoko Tanaka
-
Publication number: 20040071011Abstract: A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor substrate between the second diffusion region and a third diffusion region, and a second gate electrode provided on the second insulating film are included, wherein the first and second diffusion regions, first insulating film, and first gate electrode constitute a first memory cell, while the second and third diffusion regions, second insulating film, and second gate electrode constitute a second memory cell. The first and second gate electrodes are connected in common to form a word line electrode. The first and third diffusion regions are connected to first and second read bit lines disposed on a layer overlying the semiconductor substrate.Type: ApplicationFiled: August 27, 2003Publication date: April 15, 2004Applicant: NEC Electronics CorporationInventors: Teiichiro Nishizaka, Isami Sakai, Akira Yoshino, Shinichi Kawai, Kiyokazu Ishige, Tomohiro Hamajima, Motoko Tanaka
-
Patent number: 6677196Abstract: A semiconductor memory device is provided, which makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric. This device comprises a memory cell section including floating-gate type transistors and a capacitor section including capacitors. The memory cell section and the capacitor section are formed on a semiconductor substrate. Each of the transistors has a first gate dielectric, a floating gate, a second gate dielectric, and a control gate. Each of the capacitors has a lower electrode, a capacitor dielectric, and an upper electrode. A first part of the capacitors is/are designed to be applied with a first voltage and a second part thereof is/are applied with a second voltage on operation, where the first voltage is lower than the second voltage. Each of the first part of the capacitors has a recess formed on the lower electrode, thereby increasing its capacitance.Type: GrantFiled: November 26, 2002Date of Patent: January 13, 2004Assignee: NEC Electronics CorporationInventor: Kiyokazu Ishige
-
Publication number: 20030075750Abstract: A semiconductor memory device is provided, which makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric. This device comprises a memory cell section including floating-gate type transistors and a capacitor section including capacitors. The memory cell section and the capacitor section are formed on a semiconductor substrate. Each of the transistors has a first gate dielectric, a floating gate, a second gate dielectric, and a control gate. Each of the capacitors has a lower electrode, a capacitor dielectric, and an upper electrode. A first part of the capacitors is/are designed to be applied with a first voltage and a second part thereof is/are applied with a second voltage on operation, where the first voltage is lower than the second voltage. Each of the first part of the capacitors has a recess formed on the lower electrode, thereby increasing its capacitance.Type: ApplicationFiled: November 26, 2002Publication date: April 24, 2003Applicant: NEC CorporationInventor: Kiyokazu Ishige
-
Patent number: 6538927Abstract: The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lover erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole. However, when only some memory cells of a group have a higher erase speed, an excessive erase requiring electric charge supply occurs only in some memories and accordingly, it is possible to rapidly complete the data.Type: GrantFiled: June 26, 2002Date of Patent: March 25, 2003Assignee: NEC CorporationInventors: Kazuhiko Sanada, Kenji Saitou, Kiyokazu Ishige, Hitoshi Nakamura
-
Patent number: 6515326Abstract: A semiconductor memory device is provided, which makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric. This device comprises a memory cell section including floating-gate type transistors and a capacitor section including capacitors. The memory cell section and the capacitor section are formed on a semiconductor substrate. Each of the transistors has a first gate dielectric, a floating gate, a second gage dielectric, and a control gate. Each of the capacitors has a lower electrode, a capacitor dielectric, and an upper electrode. A first part of the capacitors is/are designed to be applied with a first voltage and a second part thereof is/are applied with a second voltage on operation, where the first voltage is lower than the second voltage. Each of the first part of the capacitors has a recess formed on the lower electrode, thereby increasing its capacitance.Type: GrantFiled: June 25, 2001Date of Patent: February 4, 2003Assignee: NEC CorporationInventor: Kiyokazu Ishige
-
Patent number: 6503797Abstract: The present invention prevents a charge-up during a wiring layer etching in a nonvolatile semiconductor storage apparatus, having a floating gate and a control gate to which both of positive and negative voltages are applied during a memory cell operation, by providing a current path from the control gate to a substrate via a charge-up preventing element. A first well is formed in the substrate. A second well is formed in the first well. The charge-up preventing element is formed in the second well. The substrate and second well are of one conductive type (p or n) and the first well and charge-up preventing element are of the other conductive type. Before memory cell operation, the control gate is disconnected from the charge-up preventing element.Type: GrantFiled: August 17, 2001Date of Patent: January 7, 2003Assignee: NEC CorporationInventor: Kiyokazu Ishige
-
Patent number: 6498753Abstract: The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lower erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole.Type: GrantFiled: August 31, 2001Date of Patent: December 24, 2002Assignee: NEC CorporationInventors: Kazuhiko Sanada, Kenji Saitou, Kiyokazu Ishige, Hitoshi Nakamura
-
Patent number: 6396098Abstract: There is provided a semiconductor memory device including a semiconductor substrate, a floating gate type transistor formed on the semiconductor substrate, acting as a memory cell of the semiconductor memory device, and a charge pump circuit formed on the semiconductor substrate. The transistor includes (a) a first gate insulating film formed on the semiconductor substrate, (b) a floating gate electrode formed on the first gate insulating film, (c) a second gate insulating film formed on the floating gate electrode, and (d) a control gate electrode formed on the second gate insulating film. The charge pump circuit includes (a) a plurality of diode devices formed on a third insulating layer formed on the semiconductor substrate, and electrically connected with each other in series, and (b) a plurality of capacitors each of which is electrically connected to a terminal of each of the diode devices.Type: GrantFiled: May 30, 1997Date of Patent: May 28, 2002Assignee: NEC CorporationInventor: Kiyokazu Ishige
-
Patent number: 6392268Abstract: The present invention prevents a charge-up during a wiring layer etching in a nonvolatile semiconductor storage apparatus having a floating gate and a control gate to which both of positive and negative voltages are applied during a memory cell operation. On a semiconductor substrate 51 of a first conductive type, a first well 52 of a second conductive type is formed to oppose to the first conductive type. In the first well 52, a second well 53 of the first conductive type is formed. On a main surface of the second well 53 is formed a composite gate 8 consisting of a first gate insulation film 4, a floating gate 5, a second gate insulation film 6, and a control gate 7 which are successively layered. On a surface of the second well 53 are formed by way of ion implantation, a source, a drain, and a charge-up preventing element diffusion layer 18 of the second conductive type.Type: GrantFiled: September 17, 1998Date of Patent: May 21, 2002Assignee: NEC CorporationInventor: Kiyokazu Ishige
-
Publication number: 20020011624Abstract: A nonvolatile semiconductor memory device and a method of fabricating the device are provided that allow the use of dry etching when removing the ONO film and that eliminate the danger of etching the silicon substrate in the gate oxide film formation areas even in the event of over-etching.Type: ApplicationFiled: September 18, 2001Publication date: January 31, 2002Applicant: NEC CorporationInventor: Kiyokazu Ishige
-
Publication number: 20020008995Abstract: The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lower erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole.Type: ApplicationFiled: August 31, 2001Publication date: January 24, 2002Inventors: Kazuhiko Sanada, Kenji Saitou, Kiyokazu Ishige, Hitoshi Nakamura
-
Publication number: 20010054736Abstract: A semiconductor memory device is provided, which makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric. This device comprises a memory cell section including floating-gate type transistors and a capacitor section including capacitors. The memory cell section and the capacitor section are formed on a semiconductor substrate. Each of the transistors has a first gate dielectric, a floating gate, a second gate dielectric, and a control gate. Each of the capacitors has a lower electrode, a capacitor dielectric, and an upper electrode. A first part of the capacitors is/are designed to be applied with a first voltage and a second part thereof is/are applied with a second voltage on operation, where the first voltage is lower than the second voltage. Each of the first part of the capacitors has a recess formed on the lower electrode, thereby increasing its capacitance.Type: ApplicationFiled: June 25, 2001Publication date: December 27, 2001Inventor: Kiyokazu Ishige
-
Publication number: 20010055847Abstract: The present invention prevents a charge-up during a wiring layer etching in a nonvolatile semiconductor storage apparatus having a floating gate and a control gate to which both of positive and negative voltages are applied during a memory cell operation.Type: ApplicationFiled: August 17, 2001Publication date: December 27, 2001Applicant: NEC CORPORATIONInventor: Kiyokazu Ishige
-
Publication number: 20010052616Abstract: The present invention prevents a charge-up during a wiring layer etching in a nonvolatile semiconductor storage apparatus having a floating gate and a control gate to which both of positive and negative voltages are applied during a memory cell operation.Type: ApplicationFiled: September 17, 1998Publication date: December 20, 2001Inventor: KIYOKAZU ISHIGE
-
Patent number: 6330191Abstract: The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lower erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole.Type: GrantFiled: November 29, 2000Date of Patent: December 11, 2001Assignee: NEC CorporationInventors: Kazuhiko Sanada, Kenji Saitou, Kiyokazu Ishige, Hitoshi Nakamura