Patents by Inventor Kiyokazu Nakagawa
Kiyokazu Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240112906Abstract: An object is to provide a manufacturing method of an insulation film in which no heating at high temperature is necessary. The manufacturing method of the insulation film includes a deposition process, a heating process and an exposure process. In the deposition process, a material is deposited on a substrate 11. In the heating process, the substrate 11 is heated at a temperature equal to or higher than 85° C. to equal to or lower than 450° C. In the exposure process, by irradiating a surface SA2 of a deposition material layer 12 on the substrate 11 with a plasma 82 containing hydrogen radicals, hydrogen is made to diffuse into the structure of the deposition material layer 12 and bind with components of the deposition material layer 12. A product of an irradiation time and a density of the radicals formed by the plasma 82 is equal to or higher than 25×1014 min·pcs/cm3.Type: ApplicationFiled: December 2, 2021Publication date: April 4, 2024Applicant: ABIT TECHNOLOGIES CO., LTDInventor: Kiyokazu NAKAGAWA
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Patent number: 10176981Abstract: If a SiO2 film is formed on a semiconductor substrate using TEOS (tetraethylorthosilicate: Si(OC2H5)4), carbon (C) may be mixed in the SiO2 film in some cases. In a SiO2 film, carbon may function as fixed charges. For example, if carbon (C) is mixed in a SiO2 film as a gate insulating film of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the gate threshold voltage (Vth) may fluctuate. A semiconductor device using a gallium nitride semiconductor layer is provided. The semiconductor device includes: a silicon dioxide film that is provided at least partially in direct contact with the gallium nitride semiconductor layer and has impurity atoms, wherein the silicon dioxide film contains as the impurity atoms: carbon at concentration higher than 0 cm?3 and lower than 2E+18 cm?3; and gallium at concentration equal to or lower than 1E+17 cm?3.Type: GrantFiled: March 1, 2018Date of Patent: January 8, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Katsunori Ueno, Kiyokazu Nakagawa
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Publication number: 20180190487Abstract: If a SiO2 film is formed on a semiconductor substrate using TEOS (tetraethylorthosilicate: Si(OC2H5)4), carbon (C) may be mixed in the SiO2 film in some cases. In a SiO2 film, carbon may function as fixed charges. For example, if carbon (C) is mixed in a SiO2 film as a gate insulating film of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the gate threshold voltage (Vth) may fluctuate. A semiconductor device using a gallium nitride semiconductor layer is provided. The semiconductor device includes: a silicon dioxide film that is provided at least partially in direct contact with the gallium nitride semiconductor layer and has impurity atoms, wherein the silicon dioxide film contains as the impurity atoms: carbon at concentration higher than 0 cm?3 and lower than 2E+18 cm?3; and gallium at concentration equal to or lower than 1E+17 cm?3.Type: ApplicationFiled: March 1, 2018Publication date: July 5, 2018Inventors: Katsunori UENO, Kiyokazu NAKAGAWA
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Patent number: 9972499Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a front surface and a back surface; forming a transition metal layer on a surface of the semiconductor substrate; and exposing the semiconductor substrate having the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves, to cause the transition metal layer to generate heat. During exposure of the semiconductor substrate, a portion of the semiconductor substrate contacting the transition metal layer is heated by a transfer of heat from the transition metal layer and, at an interface of the transition metal layer and the semiconductor substrate, an ohmic contact is formed by reaction of the transition metal layer and the semiconductor substrate, such as to form a transition metal silicide when the semiconductor substrate is silicon carbide. The ohmic contact provides a lower contact resistivity and device properties can be prevented from degrading.Type: GrantFiled: March 9, 2016Date of Patent: May 15, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Haruo Nakazawa, Masaaki Ogino, Tsunehiro Nakajima, Kenichi Iguchi, Masaaki Tachioka, Kiyokazu Nakagawa
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Publication number: 20160189967Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a front surface and a back surface; forming a transition metal layer in a surface of the semiconductor substrate; and exposing the semiconductor substrate having the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves, to cause the transition metal layer to generate heat, Thus, during the exposure of the semiconductor substrate, a portion of the semiconductor substrate contacting the transition metal layer is heated by a transfer of heat from the transition metal layer and, at an interface of the transition metal layer and the semiconductor substrate, an ohmic contact is formed by reaction of the transition metal layer and the semiconductor substrate, such as to form a transition metal silicide when the semiconductor substrate is silicon carbide. The ohmic contact provides a lower contact resistivity and device properties can be prevented from degrading.Type: ApplicationFiled: March 9, 2016Publication date: June 30, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventors: Haruo NAKAZAWA, Masaaki OGINO, Tsunehiro NAKAJIMA, Kenichi IGUCHI, Masaaki TACHIOKA, Kiyokazu NAKAGAWA
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Patent number: 8304810Abstract: In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.Type: GrantFiled: July 20, 2009Date of Patent: November 6, 2012Assignee: Renesas Electronics CorporationInventors: Nobuyuki Sugii, Kiyokazu Nakagawa, Shinya Yamaguchi, Masanobu Miyao
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Publication number: 20090283839Abstract: In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.Type: ApplicationFiled: July 20, 2009Publication date: November 19, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Nobuyuki SUGII, Kiyokazu NAKAGAWA, Shinya YAMAGUCHI, Masanobu MIYAO
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Patent number: 7579229Abstract: In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.Type: GrantFiled: January 22, 2008Date of Patent: August 25, 2009Assignee: Renesas Technology Corp.Inventors: Nobuyuki Sugii, Kiyokazu Nakagawa, Shinya Yamaguchi, Masanobu Miyao
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Publication number: 20080206961Abstract: In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.Type: ApplicationFiled: January 22, 2008Publication date: August 28, 2008Inventors: Nobuyuki Sugii, Kiyokazu Nakagawa, Shinya Yamaguchi, Masanobu Miyao
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Publication number: 20080135890Abstract: Disclosed is a manufacturing method for forming a FET on a glass substrate at low temperatures. A polycrystalline silicon layer 2 is formed on a glass substrate 1, germanium layers 11, 12 are formed on the polycrystalline silicon layer in regions that are to become a source and a drain, ions serving as a dopant are implanted into at least the germanium layers, and annealing is subsequently applied to thereby cause the implanted dopant to diffuse into the polycrystalline. silicon layer, form a source region S and a drain region D and crystallize the germanium layers. Alternatively, the dopant is implanted also into the polycrystalline silicon layer at such a dosage that will not cause the polycrystalline silicon layer to become amorphous. Annealing for crystallizing the germanium is subsequently carried out. Annealing may be performed in the neighborhood of 500° C.Type: ApplicationFiled: May 31, 2005Publication date: June 12, 2008Applicant: YAMANASHI TLO CO., LTD.Inventors: Kiyokazu Nakagawa, Keisuke Arimoto, Minoru Mitsui
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Publication number: 20080111134Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.Type: ApplicationFiled: January 4, 2008Publication date: May 15, 2008Inventors: Shinya Yamaguchi, Masanobu Miyao, Nobuyuki Sugii, Seang-kee Park, Kiyokazu Nakagawa
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Patent number: 7317207Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.Type: GrantFiled: June 7, 2005Date of Patent: January 8, 2008Assignee: Hitachi, Ltd.Inventors: Shinya Yamaguchi, Masanobu Miyao, Nobuyuki Sugii, Seang-kee Park, Kiyokazu Nakagawa
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Publication number: 20050230683Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.Type: ApplicationFiled: June 7, 2005Publication date: October 20, 2005Inventors: Shinya Yamaguchi, Masanobu Miyao, Nobuyuki Sugii, Seang-kee Park, Kiyokazu Nakagawa
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Patent number: 6903372Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.Type: GrantFiled: October 30, 2000Date of Patent: June 7, 2005Assignee: Hitachi, Ltd.Inventors: Shinya Yamaguchi, Masanobu Miyao, Nobuyuki Sugii, Seang-kee Park, Kiyokazu Nakagawa
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Patent number: 6888162Abstract: An electronic apparatus employs a polycrystalline semiconductor thin film structure formed of an insulating substrate and a plurality of polycrystalline layers laminated on the insulating substrate. A plurality of transistors are formed at the surface of the polycrystalline semiconductor thin film structure, each transistor being formed in a region of one of a plurality of crystal grains disseminated on the surface of the polycrystalline layers. A number of crystal grains in each of the polycrystalline layers is gradually reduced from a lower layer to an upper layer.Type: GrantFiled: January 30, 2003Date of Patent: May 3, 2005Assignee: Hitachi, Ltd.Inventors: Shinya Yamaguchi, Masanobu Miyao, Kiyokazu Nakagawa, Nobuyuki Sugii
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Publication number: 20050017236Abstract: In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer 1 having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.Type: ApplicationFiled: August 18, 2004Publication date: January 27, 2005Inventors: Nobuyuki Sugii, Kiyokazu Nakagawa, Shinya Yamaguchi, Masanobu Miyao
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Patent number: 6727514Abstract: At least one of a semiconductor thin-film for forming a picture display portion and a semiconductor thin-film for forming a peripheral circuit portion, which are accumulated on one common insulative substrate, is constructed with a semiconductor thin-film having a plural number of semiconductor crystalline portions formed to be divided and disposed in a matrix-like, and TFTs are provided in the semiconductor thin-film by bringing those semiconductor single crystal portions into active portions thereof. For that purpose, a crystallization accelerating material is adhered at the position of lattice points of a matrix and is treated with heating process, for forming the single crystal portions disposed in the matrix-like manner, so as to form the TFTs on the surface thereof, thereby completing the thin-film semiconductor integrated circuit device.Type: GrantFiled: March 20, 2001Date of Patent: April 27, 2004Assignee: Hitachi, Ltd.Inventors: Seong-kee Park, Kiyokazu Nakagawa, Nobuyuki Sugii, Shinya Yamaguchi
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Publication number: 20030132437Abstract: The present invention provides a method for crystallizing a polycrystalline silicon layers used for the material of thin film transistors at large size (more than 8 microns) with crystal orientation aligned to a specific orientation, and for controlling the positioning of crystal grains at high precision. On a polycrystalline silicon layer, projections at regular intervals are formed by using anisotropic etching and a photomask. The tip of projections is comprised of single crystal silicon of a specific crystal orientation selectively left by the anisotropic etching, which is a candidate for nuclei of amorphous silicon to be deposited thereon. By iterating above process at a plurality of times, and by gradually enlarging the interval, span, size and height of projections, the size of crystal grains of silicon at the surface may be enlarged to the extent required. Thereby silicon crystal grains of large grains with crystal orientation aligned may be formed at controllable positions.Type: ApplicationFiled: January 30, 2003Publication date: July 17, 2003Applicant: Hitachi, Ltd.Inventors: Shinya Yamaguchi, Masanobu Miyao, Kiyokazu Nakagawa, Nobuyuki Sugii
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Patent number: 6545294Abstract: The present invention provides an apparatus having a semiconductor device including a plurality of transistors formed on respective single crystal silicon regions of enlarged grain size. On a polycrystalline silicon layer, projections at regular intervals are formed by using anisotropic etching and a photomask. The tips of projections are composed of single crystal silicon of a specific crystal orientation selectively left by the anisotropic etching, which is a candidate for nuclei of amorphous silicon to be deposited thereon. By iterating the above process a plurality of times, and by gradually enlarging the pitch, span, size and height of projections, the size of the crystal grains of silicon at the surface may be enlarged to the extent required. Thereby, silicon crystal grains of large grain size with the crystal orientation aligned may be formed at controllable positions.Type: GrantFiled: May 16, 2000Date of Patent: April 8, 2003Assignee: Hitachi, Ltd.Inventors: Shinya Yamaguchi, Masanobu Miyao, Kiyokazu Nakagawa, Nobuyuki Sugii
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Patent number: 6529304Abstract: Configurations of a light signal communication apparatus and an optical communication system suitable for speeding-up of the transmission of information based on a light signal and an increase in the capacity for the information transmission are disclosed. On the light signal transmitting side, excitation light is supplied to an active medium in accordance with a transmission signal to cause induced emission within the active medium, thereby generating signal light. The excitation light causes spontaneously-emitted light to fall on a semiconductor layer, and a voltage pulse corresponding to transmission information is applied to modulate the refractive index of the semiconductor layer, thereby Bragg-reflecting a specific wavelength component, after which it is sent to the active medium as the excitation light. The Bragg reflection and induced emission incident to it exhibit excellent response to a voltage signal having a pulse width of 1×10−9 seconds or less.Type: GrantFiled: September 17, 1999Date of Patent: March 4, 2003Assignee: Hitachi, Ltd.Inventors: Yoshinobu Kimura, Masanobu Miyao, Kiyokazu Nakagawa, Nobuyuki Sugii, Takuya Maruizumi