Patents by Inventor Kiyomi Koyama
Kiyomi Koyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7047094Abstract: A computer implemented method for LSI mask manufacturing stores performance information of a lithography unit, connected to a network, in a lithography unit database. The method receives a lithography data and a lithography reservation condition from a user terminal connected to the network. The method stores the lithography data in a lithography data database. The method searches for a lithography unit matching to the lithography reservation condition, generating a list of lithography units, and sending the list to the user terminal. In addition, the method receives information of a lithography unit specified by the user terminal and sending a lithography request to the lithography unit specified by the user terminal.Type: GrantFiled: March 26, 2003Date of Patent: May 16, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Kiyomi Koyama
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Publication number: 20030188289Abstract: A computer implemented method for LSI mask manufacturing stores performance information of a lithography unit, connected to a network, in a lithography unit database. The method receives a lithography data and a lithography reservation condition from a user terminal connected to the network. The method stores the lithography data in a lithography data database. The method searches for a lithography unit matching to the lithography reservation condition, generating a list of lithography units, and sending the list to the user terminal. In addition, the method receives information of a lithography unit specified by the user terminal and sending a lithography request to the lithography unit specified by the user terminal.Type: ApplicationFiled: March 26, 2003Publication date: October 2, 2003Inventor: Kiyomi Koyama
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Patent number: 6447355Abstract: There is provided an impregnated-type cathode substrate comprising a large particle diameter low porosity region and a small particle diameter high porosity region which is provided in a side of an electron emission surface of the large particle diameter low porosity region and has an average particle diameter smaller than an average particle diameter of the large particle diameter low pore region and a porosity higher than a porosity of the large particle diameter low porosity region, the impregnated-type cathode being impregnated with an electron emission substance.Type: GrantFiled: December 17, 1999Date of Patent: September 10, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Eiichirou Uda, Toshiharu Higuchi, Osamu Nakamura, Kiyomi Koyama, Sadao Matsumoto, Yoshiaki Ouchi, Kazuo Kobayashi, Takashi Sudo, Katsuhisa Homma
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Patent number: 6304024Abstract: There is provided an impregnated-type cathode substrate comprising a large particle diameter low porosity region and a small particle diameter high porosity region which is provided in a side of an electron emission surface of the large particle diameter low porosity region and has an average particle diameter smaller than an average particle diameter of the large particle diameter low pore region and a porosity higher than a porosity of the large particle diameter low porosity region, the impregnated-type cathode being impregnated with an electron emission substance.Type: GrantFiled: December 17, 1999Date of Patent: October 16, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Eiichirou Uda, Toshiharu Higuchi, Osamu Nakamura, Kiyomi Koyama, Sadao Matsumoto, Yoshiaki Ouchi, Kazuo Kobayashi, Takashi Sudo, Katsuhisa Homma
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Patent number: 6077310Abstract: Pattern data that is an object of correction is divided into an area on which correction is made using correction values that have been obtained in advance for patterns and their respective layouts and an area on which correction is made on the basis of correction values calculated by a simulator. For example, simulation-based correction is made on a gate layer in a memory, while rule-based correction is made on a gate layer in the other area than the memory on the basis of rules for active gate width only. After being subjected to the correction, the areas are combined.Type: GrantFiled: January 29, 1999Date of Patent: June 20, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Kazuko Yamamoto, Sachiko Miyama, Kiyomi Koyama, Soichi Inoue
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Patent number: 6047116Abstract: In a method of generating from design data the exposure data necessary for a multistage-deflection charged beam exposure device that has a main deflector and a sub-deflector and forms a pattern, before a shape larger than the size of a minimum subfield area is divided during the generation of subfield exposure data, the process of dividing the shape into shapes equal to or smaller than the size of a subfield area and restructuring the shape is performed. Moreover, after the overlapping cell arrays in the design data are changed into a cell array structure preventing the cell arrays from overlapping, the resulting cell arrays are subjected to a hierarchical shape data operation process and a formatting process, including compression, subfield division, and frame division. This makes it possible to reduce the amount of data supplied without increasing the time required to converting the design data into exposure data supplied to the charged beam exposure device.Type: GrantFiled: March 18, 1998Date of Patent: April 4, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Eiji Murakami, Hitoshi Higurashi, Shigehiro Hara, Kiyomi Koyama, Takayuki Abe
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Patent number: 6034469Abstract: There is provided an impregnated-type cathode substrate comprising a large particle diameter low porosity region and a small particle diameter high porosity region which is provided in a side of an electron emission surface of the large particle diameter low porosity region and has an average particle diameter smaller than an average particle diameter of the large particle diameter low pore region and a porosity higher than a porosity of the large particle diameter low porosity region, the impregnated-type cathode being impregnated with an electron emission substance.Type: GrantFiled: December 9, 1997Date of Patent: March 7, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Eiichirou Uda, Toshiharu Higuchi, Osamu Nakamura, Kiyomi Koyama, Sadao Matsumoto, Yoshiaki Ouchi, Kazuo Kobayashi, Takashi Sudo, Katsuhisa Homma
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Patent number: 6004701Abstract: In a Levenson photomask design method of partially forming a plurality of opening patterns for passing incident light in a light-shielding film for shielding the incident light, and arranging, on some patterns, phase shifters, line segment pairs of different patterns which are adjacent to each other within a predetermined distance R are extracted in units of line segments obtained by dividing the patterns. A pattern within a predetermined distance S from the central point of the opposite region of a line segment pair of interest in a direction perpendicular to the line segments is obtained. The obtained pattern is subjected to a process simulation to obtain resolution easiness representing the easiness in resolving the adjacent patterns. On the basis of the resolution easiness obtained for the adjacent pattern pair within the distance R, a phase shifter is arranged in ascending order of resolution easiness to give a phase difference.Type: GrantFiled: March 24, 1998Date of Patent: December 21, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Taiga Uno, Kiyomi Koyama, Kazuko Yamamoto, Satoshi Tanaka, Sachiko Kobayashi, Koji Hashimoto
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Patent number: 5879844Abstract: Pattern data that is an object of correction is divided into an area on which correction is made using correction values that have been obtained in advance for patterns and their respective layouts and an area on which correction is made on the basis of correction values calculated by a simulator. For example, simulation-based correction is made on a gate layer in a memory, while rule-based correction is made on a gate layer in the other area than the memory on the basis of rules for active gate width only. After being subjected to the correction, the areas are combined.Type: GrantFiled: December 20, 1996Date of Patent: March 9, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Kazuko Yamamoto, Sachiko Miyama, Kiyomi Koyama, Soichi Inoue
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Patent number: 5795683Abstract: A method for designing a photomask, used in photolithography using partially coherent incident light, the photomask having a substrate on which a plurality of transparent regions and opaque regions are formed, the transparent regions including a phase shifter for providing the incident light transmitting through the transparent regions with a phase difference, the method comprising the steps of extracting combinations of patterns adjacent to each other within a distance of a threshold value S2 as adjacent pairs from patterns corresponding to the transparent regions, calculating difficulty of correction of the adjacent pairs, sorting the adjacent pairs in an descending order of the difficulty of correction, connecting the patterns in the adjacent pairs to one another, such that a pair of adjacent patterns are not connected to each other and loop cut is performed if a closed loop is formed by connecting the adjacent patterns, and a pair of adjacent patterns are logically connected if a closed loop is not formedType: GrantFiled: March 27, 1996Date of Patent: August 18, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Taiga Uno, Kiyomi Koyama, Kazuko Yamamoto
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Patent number: 5761075Abstract: Method and apparatus for designing the photomask in the course of designing the Levenson-type phase shift mask, capable of automatically arranging the shifter, of not causing a contradictory spot in a circuit designing stage and of automatically forming a final layout achieving maximum integrity. The method includes the steps of: forming symbolic layout data in which a distance between adjacent clear areas is set to an arbitrary value; determining regions having a mutual phase difference 0.degree. or 180.degree. of light transmitting through adjacent patterns corresponding to the clear areas in the symbolic layout data; executing compaction of the symbolic layout in a manner that design rule S1 is adopted to the clear areas neighboring with the phase difference of 180.degree. and design rule S2 is adopted to the clear areas neighboring with the phase difference of 0.degree.; and forming mask layout data such that S1 is less than S2.Type: GrantFiled: May 31, 1996Date of Patent: June 2, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Kazuko Oi, Kiyomi Koyama
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Patent number: 5541025Abstract: Method and apparatus for designing the photomask in the course of designing the Levenson-type phase shift mask, capable of automatically arranging the shifter, of not causing a contradictory spot in a circuit designing stage and of automatically forming a final layout achieving maximum integrity. The method includes the steps of: forming symbolic layout data in which a distance between adjacent clear areas is set to an arbitrary value; determining regions having a mutual phase difference 0.degree. or 180.degree. of light transmitting through adjacent patterns corresponding to the clear areas in the symbolic layout data; executing compaction of the symbolic layout in a manner that design rule S1 is adopted to the clear areas neighboring with the phase difference of 180.degree. and design rule S2 is adopted to the clear areas neighboring with the phase difference of 0.degree.; and forming mask layout data such that S1 is less than S2.Type: GrantFiled: December 28, 1994Date of Patent: July 30, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Kazuko Oi, Kiyomi Koyama
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Patent number: 5538815Abstract: A method for designing a phase-shifting mask in a manner that a phase shifter of the mask is arranged so that a phase difference between light transmitted through clear areas with the phase shifter and light transmitted through clear areas without the phase shifter is set to 180.degree. or further different combination of phase differences being such as 0.degree., 90.degree. and 270.degree.. The method includes the steps of: defining a threshold value in a manner that the threshold value falls within a range which is possible to resolve using the phase-shifting masks; measuring a distance between neighboring shapes of the clear area; storing adjacent relationship of the neighboring shapes whose distance is less than the threshold; and automatically placing the phase shifter on one of the neighboring shapes of the clear areas in a manner that mutually neighboring clear area have an opposite phase to each other.Type: GrantFiled: September 14, 1993Date of Patent: July 23, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Kazuko Oi, Shigehiro Hara, Kiyomi Koyama, Koji Hashimoto, Shinichi Ito, Katsuya Okumura
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Patent number: 4914304Abstract: In an electron beam exposure system, an electron beam emitted from an electron gun is shaped by first and second beam-shaping aperture masks and is projected on a target to draw a predetermined pattern. The predetermined pattern consists of rectangular segment patterns, right-angled triangular segment patterns and predetermined identical segment patterns. Thus, the first aperture mask has a main rectangular aperture and additional predetermined apertures and the second aperture mask has a combination of rectangular and hexagonal apertures which contact each other at one side. The rectangular segment pattern is exposed by the beam passing through the main aperture of the first aperture mask and the rectangular aperture of second aperture and the triangular segment pattern is exposed by the beam passing through the main aperture of the first aperture mask and the triangular aperture of the second aperture mask.Type: GrantFiled: August 14, 1989Date of Patent: April 3, 1990Assignee: Kabushiki Kaisha ToshibaInventor: Kiyomi Koyama
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Patent number: 4538232Abstract: A coordinate data memory is provided, in which a plurality of coordinate data representing partial patterns constituting a pattern to be drawn on a semiconductor wafer are stored. The coordinate data are supplied from the coordinate data memory to a plurality of coordinate data converters. The data converters convert coordinate data into address data by which pattern memories are specified respectively. Bit patterns are formed according to the address data in the pattern memories, respectively. The bit patterns of the pattern memories are synchronously read out bit by bit and synthesized in a logic gate circuit, and the resultant pattern is supplied to a blanking circuit bit by bit.Type: GrantFiled: April 21, 1982Date of Patent: August 27, 1985Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventor: Kiyomi Koyama
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Patent number: 4531191Abstract: Bit pattern data stored in an external memory unit is read out under the control of a microprocessor for being compressed in a data compressing unit and then stacked in a memory unit. At the time of storing data in the memory unit, all the stripe data constituting one chip frame are written in a state capable of being made high speed sequentially accessible at the time of the read-out without need of dividing a memory bank into portions for the individual stripes but by continuously using the address space covering the entire memory areas. This is effected by a memory management unit and a memory module management unit provided in the memory unit.Type: GrantFiled: December 28, 1981Date of Patent: July 23, 1985Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventor: Kiyomi Koyama