Patents by Inventor Kiyomi Naruke
Kiyomi Naruke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11569256Abstract: A device includes a stack above a substrate in a first direction perpendicular to a surface of the substrate, the stack including conductive layers; a semiconductor layer neighboring the stack in a second direction parallel to the surface of the substrate; a memory layer between the first stack and the semiconductor layer; memory cells between the conductive layers and the semiconductor layer; a first transistor connected between one end of the semiconductor layer in a third direction parallel to the surface of the substrate and crossing the second direction and a first interconnect in the first direction; and a second transistor connected between the other end of the semiconductor layer and a second interconnect in the first direction.Type: GrantFiled: March 12, 2020Date of Patent: January 31, 2023Assignee: Kioxia CorporationInventors: Kiyomi Naruke, Shinichiro Shiratake, Mutsumi Okajima, Hidetoshi Saito, Hirofumi Inoue
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Publication number: 20210091108Abstract: According to one embodiment, a device includes a stack above a substrate in a first direction perpendicular to a surface of the substrate, the stack including conductive layers; a semiconductor layer neighboring the stack in a second direction parallel to the surface of the substrate; a memory layer between the first stack and the semiconductor layer; memory cells between the conductive layers and the semiconductor layer; a first transistor connected between one end of the semiconductor layer in a third direction parallel to the surface of the substrate and crossing the second direction and a first interconnect in the first direction; and a second transistor connected between the other end of the semiconductor layer and a second interconnect in the first direction.Type: ApplicationFiled: March 12, 2020Publication date: March 25, 2021Applicant: Kioxia CorporationInventors: Kiyomi NARUKE, Shinichiro Shiratake, Mutsumi Okajima, Hidetoshi Saito, Hirofumi Inoue
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Patent number: 8873292Abstract: A nonvolatile semiconductor memory device according to one embodiment includes: memory cells; word lines connected to the memory cells; and a control circuit configured to control a data read operation. When controlling the data read operation, the control circuit applies one of read voltages to a selected word line, applies a first read pass voltage to a first non-selected word line connected to one of data-written memory cells, and applies a second read pass voltage to a second non-selected word line connected to a non-written memory cell. Each of the read voltages is set to a voltage between two threshold voltage distributions. The first read pass voltage is set so that the data-written memory cells become conductive. The second read pass voltage is set so as to be lower than a highest read voltage, the highest read voltage being the highest voltage among the read voltages.Type: GrantFiled: March 20, 2012Date of Patent: October 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hidefumi Nawata, Kiyomi Naruke
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Patent number: 8533549Abstract: A memory system includes: a memory chip group including n chips of a nonvolatile semiconductor memory dividedly managed for each of unit areas having predetermined sizes, an unit area of one chip among the n chips storing an error correction code for a group including unit areas in the other n?1 chips associated with the unit area, and the chip that stores the error correction code being different for each of positions of the unit areas; and an access-destination calculating unit that designates, when data in the unit areas is rewritten, the unit area in which the error correction code of data is stored as a writing destination of rewriting data, and designates an unit area in which data before rewriting is stored as a storage destination of a new error correction code.Type: GrantFiled: February 1, 2010Date of Patent: September 10, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Kondo, Kiyomi Naruke, Naoyuki Shigyo
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Publication number: 20130077404Abstract: A nonvolatile semiconductor memory device according to one embodiment includes: memory cells; word lines connected to the memory cells; and a control circuit configured to control a data read operation. When controlling the data read operation, the control circuit applies one of read voltages to a selected word line, applies a first read pass voltage to a first non-selected word line connected to one of data-written memory cells, and applies a second read pass voltage to a second non-selected word line connected to a non-written memory cell. Each of the read voltages is set to a voltage between two threshold voltage distributions. The first read pass voltage is set so that the data-written memory cells become conductive. The second read pass voltage is set so as to be lower than a highest read voltage, the highest read voltage being the highest voltage among the read voltages.Type: ApplicationFiled: March 20, 2012Publication date: March 28, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Hidefumi Nawata, Kiyomi Naruke
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Patent number: 8319270Abstract: A non-volatile memory of a semiconductor device has a tunnel insulation film provided on the active area; a floating gate electrode provided on the tunnel insulation film; a control gate electrode provided over the floating gate electrode; and an inter-electrode insulation film provided between the floating gate electrode and the control gate electrode, wherein, in a section of the non-volatile memory cell in a channel width direction, a dimension of a top face of the active area in the channel width direction is equal to or less than a dimension of a top face of the tunnel insulation film in the channel width direction, and the dimension of the top face of the tunnel insulation film in the channel width direction is less than a dimension of a bottom face of the floating gate electrode in the channel width direction.Type: GrantFiled: December 18, 2009Date of Patent: November 27, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Mutsuo Morikado, Kiyomi Naruke, Hiroaki Tsunoda, Tohru Maruyama, Fumitaka Arai
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Publication number: 20120250419Abstract: In one embodiment, method of controlling a semiconductor nonvolatile memory device includes determining data written to an adjacent memory cell which is adjacent to a selection memory cell in memory cells configured as a matrix, the selection memory being selected by a program operation for writing the data to the selection memory, and writing the data to the selection memory with controlling an amount of charges injected into the selection memory based on a result of determining the data.Type: ApplicationFiled: September 14, 2011Publication date: October 4, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hidefumi NAWATA, Kiyomi Naruke
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Publication number: 20110198682Abstract: In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a well of a first conductivity type formed in the substrate. The device further includes a plurality of first isolation layers disposed in parallel to each other in the well, and a second isolation layer disposed in parallel to the first isolation layers in the well, a width of a substrate surface between the second isolation layer and the first isolation layers being set greater than a width of a substrate surface between the first isolation layers. The device further includes a memory cell including a gate insulator, a floating gate, an inter-gate insulator, and a control gate sequentially disposed on the well between the first isolation layers, and a dummy cell including a gate insulator, a floating gate, an inter-gate insulator, and a control gate sequentially disposed on the well between the second isolation layer and one of the first isolation layers.Type: ApplicationFiled: September 10, 2010Publication date: August 18, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kiyomi NARUKE
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Publication number: 20110024824Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer and a transistor. The transistor includes: a source region, a drain region, and a channel region provided in the semiconductor layer, the channel region being between the source and drain regions; a gate insulating film provided on the channel region; a charge layer provided on the gate insulating film, the charge layer having a side portion and a apical portion; an inter-electrode insulating film covering the side portion and the apical portion; and a control gate provided on the inter-electrode insulating film. The control gate includes: a side-portion conductive layer opposing the side portion; and an apical-portion conductive layer opposing the apical portion. The apical-portion conductive layer has a work function higher than a work function of the charge layer and higher than a work function of the side-portion conductive layer.Type: ApplicationFiled: June 22, 2010Publication date: February 3, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro SHIMURA, Takashi Izumida, Mutsuo Morikado, Kiyomi Naruke
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Publication number: 20110001180Abstract: In a nonvolatile semiconductor memory device having a plurality of nonvolatile memory cells integrated on a semiconductor substrate, each of the memory cells includes a tunnel insulating film formed on the semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, a first interelectrode insulating film formed on the upper surface of the floating gate electrode, a second interelectrode insulating film formed to cover the side surfaces of the floating gate electrode and the first interelectrode insulating film, and a control gate electrode formed on the second interelectrode insulating film.Type: ApplicationFiled: April 27, 2010Publication date: January 6, 2011Inventors: Kazunori MASUDA, Mutsuo Morikado, Kiyomi Naruke
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Publication number: 20100313101Abstract: A memory system includes: a memory chip group including n chips of a nonvolatile semiconductor memory dividedly managed for each of unit areas having predetermined sizes, an unit area of one chip among the n chips storing an error correction code for a group including unit areas in the other n?1 chips associated with the unit area, and the chip that stores the error correction code being different for each of positions of the unit areas; and an access-destination calculating unit that designates, when data in the unit areas is rewritten, the unit area in which the error correction code of data is stored as a writing destination of rewriting data, and designates an unit area in which data before rewriting is stored as a storage destination of a new error correction code.Type: ApplicationFiled: February 1, 2010Publication date: December 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeo Kondo, Kiyomi Naruke, Naoyuki Shigyo
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Publication number: 20100238725Abstract: Each of the memory cells stores multiple bits of data by way of a threshold voltage distribution having a negative value and representing an erase state, and a plurality of threshold voltage distributions each having a value higher than the threshold voltage distribution representing the erase state and representing a programming state. In a data programming operation, a control circuit applies a certain verify voltage to a control gate of one of the memory cells to be written to obtain a threshold voltage distribution higher than the threshold voltage distribution representing the erase state, thereby confirming the programming state of the memory cells. The control circuit also applies, in a data programming operation, a certain verify voltage to a control gate of one of the memory cells maintained in the erase state, thereby adjusting a lower limit value of the threshold voltage distribution representing the erase state.Type: ApplicationFiled: March 19, 2010Publication date: September 23, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kiyomi NARUKE
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Publication number: 20100155812Abstract: A non-volatile memory of a semiconductor device has a tunnel insulation film provided on the active area; a floating gate electrode provided on the tunnel insulation film; a control gate electrode provided over the floating gate electrode; and an inter-electrode insulation film provided between the floating gate electrode and the control gate electrode, wherein, in a section of the non-volatile memory cell in a channel width direction, a dimension of a top face of the active area in the channel width direction is equal to or less than a dimension of a top face of the tunnel insulation film in the channel width direction, and the dimension of the top face of the tunnel insulation film in the channel width direction is less than a dimension of a bottom face of the floating gate electrode in the channel width direction.Type: ApplicationFiled: December 18, 2009Publication date: June 24, 2010Inventors: Mutsuo Morikado, Kiyomi Naruke, Hiroaki Tsunoda, Tohru Maruyama, Fumitaka Arai
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Patent number: 7215576Abstract: In a data erasing method of a nonvolatile semiconductor memory device, cells are subjected to the processings of executing programming by applying a voltage to the cells to set their threshold values at a given level or more, erasing the cells to set their threshold values at a lower level or less, executing weak programming once on a cell whose threshold value is lower than a further lower level, by applying a lower voltage to the cell, repeating the weak programming on the cell when its threshold value is still lower than the further lower level, until the value reaches the further lower level or more, verifying whether a cell is present whose threshold value is higher than the lower level, and returning the processing to the processing of setting the threshold values of the cells at the lower level or less, when verifying that the above cell is present.Type: GrantFiled: August 30, 2005Date of Patent: May 8, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Hideo Kato, Takamichi Kasai, Kiyomi Naruke, Hiroyuki Sasaki
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Patent number: 7094652Abstract: Disclosed is a semiconductor device comprising a first transistor and a second transistor formed on a semiconductor substrate, wherein a gate side wall of the second transistor has a thickness equal to that of a gate side wall of the first transistor, wherein each of the first and second transistors has an inner low impurity diffusion region and an outer high impurity diffusion region, and wherein the size of the inner low impurity diffusion region of the second transistor along the surface of the semiconductor substrate is larger than that of the inner low impurity diffusion region of the first transistor.Type: GrantFiled: April 29, 2004Date of Patent: August 22, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Kiyomi Naruke, Kazunori Masuda
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Publication number: 20060067132Abstract: In a data erasing method of a nonvolatile semiconductor memory device, cells are subjected to the processings of executing programming by applying a voltage to the cells to set their threshold values at a given level or more, erasing the cells to set their threshold values at a lower level or less, executing weak programming once on a cell whose threshold value is lower than a further lower level, by applying a lower voltage to the cell, repeating the weak programming on the cell when its threshold value is still lower than the further lower level, until the value reaches the further lower level or more, verifying whether a cell is present whose threshold value is higher than the lower level, and returning the processing to the processing of setting the threshold values of the cells at the lower level or less, when verifying that the above cell is present.Type: ApplicationFiled: August 30, 2005Publication date: March 30, 2006Inventors: Hiroshi Watanabe, Hideo Kato, Takamichi Kasai, Kiyomi Naruke, Hiroyuki Sasaki
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Patent number: 6806540Abstract: Disclosed is a semiconductor device comprising a first transistor and a second transistor formed on a semiconductor substrate, wherein a gate side wall of the second transistor has a thickness equal to that of a gate side wall of the first transistor, wherein each of the first and second transistors has an inner low impurity diffusion region and an outer high impurity diffusion region, and wherein the size of the inner low impurity diffusion region of the second transistor along the surface of the semiconductor substrate is larger than that of the inner low impurity diffusion region of the first transistor.Type: GrantFiled: October 10, 2001Date of Patent: October 19, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Kiyomi Naruke, Kazunori Masuda
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Publication number: 20040203207Abstract: Disclosed is a semiconductor device comprising a first transistor and a second transistor formed on a semiconductor substrate, wherein a gate side wall of the second transistor has a thickness equal to that of a gate side wall of the first transistor, wherein each of the first and second transistors has an inner low impurity diffusion region and an outer high impurity diffusion region, and wherein the size of the inner low impurity diffusion region of the second transistor along the surface of the semiconductor substrate is larger than that of the inner low impurity diffusion region of the first transistor.Type: ApplicationFiled: April 29, 2004Publication date: October 14, 2004Inventors: Hiroshi Watanabe, Kiyomi Naruke, Kazunori Masuda
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Patent number: 6376295Abstract: There is disclosed a memory cell which has a diffusion layers constituting source/drain areas formed on a p-type silicon substrate surface, and a channel area formed between the diffusion layers. Above the channel area, an insulating film of a laminated structure is formed of a silicon oxide film, a silicon nitride film and a silicon oxide film. A gate electrode is formed on the upper surface of the insulating film of the laminated structure. The gate electrode is used as a word line. Moreover, an interlayer insulating film is formed between the diffusion layer and the gate electrode. By injecting hot electrons from the substrate to the silicon nitride film in the insulating film of the laminated structure, data is written. The silicon nitride film and the diffusion layer are partially overlapped in a vertical direction, and an offset portion is disposed between the silicon nitride film and the diffusion layer.Type: GrantFiled: August 3, 2000Date of Patent: April 23, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Kiyomi Naruke, Minoru Kurata, Yuuichi Tatsumi, Yasumasa Sawada
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Publication number: 20020041000Abstract: Disclosed is a semiconductor device comprising a first transistor and a second transistor formed on a semiconductor substrate, wherein a gate side wall of the second transistor has a thickness equal to that of a gate side wall of the first transistor, wherein each of the first and second transistors has an inner low impurity diffusion region and an outer high impurity diffusion region, and wherein the size of the inner low impurity diffusion region of the second transistor along the surface of the semiconductor substrate is larger than that of the inner low impurity diffusion region of the first transistor.Type: ApplicationFiled: October 10, 2001Publication date: April 11, 2002Inventors: Hiroshi Watanabe, Kiyomi Naruke, Kazunori Masuda