Abstract: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.

Abstract: A system LSI includes first and second memories, first and second buses, a bus bridge that performs signal transfer between the first and second buses, a first bus system connecting to the first bus and accessing the first or second memory, a second bus system connecting to the second bus and accessing the first or second memory, a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses and first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories.

Abstract: A computer-readable recording medium that stores therein a computer program for designing a dynamic reconfigurable circuit in which a plurality of circuit configurations are implemented with a single circuit, the computer program enabling a computer to execute: acquiring a plurality of contexts having connection information between operation devices and network modules, wherein the operation devices and network modules are disposed in clusters, and connection information among the network modules; calculating a cluster count of the clusters and an operation device count for each operation device type of the operation devices in each cluster based on the acquired plurality of contexts; generating a circuit configuration for each context in which disposition of the operation devices in each cluster and connection of the network modules are made to satisfy the calculated cluster count and operation device count; and outputting the generated circuit configuration.

Abstract: A reconfigurable circuit includes a data execution unit including a plurality of execution elements, each of which performs execution with respect to plural data upon the plural data being all in a valid state, and holds valid-state output data indicative of a result of the execution at an output node while all the plural data are in the valid state, a data selecting unit configured to connect between the execution elements in a reconfigurable manner, and a data input unit configured to supply input data to a series of execution elements to perform a series of executions, wherein a valid or invalid state of given data is specified by a valid signal accompanying and forming a pair with the given data, and the input data supplied from the data input unit to the data execution unit are fixed to valid-state constant data while the series of executions are performed.

Abstract: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.

Abstract: A system LSI includes first and second memories, first and second buses, a bus bridge that performs signal transfer between the first and second buses, a first bus system connecting to the first bus and accessing the first or second memory, a second bus system connecting to the second bus and accessing the first or second memory, a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses and first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories.

Abstract: A computer-readable recording medium that stores therein a computer program for designing a dynamic reconfigurable circuit in which a plurality of circuit configurations are implemented with a single circuit, the computer program enabling a computer to execute: acquiring a plurality of contexts having connection information between operation devices and network modules, wherein the operation devices and network modules are disposed in clusters, and connection information among the network modules; calculating a cluster count of the clusters and an operation device count for each operation device type of the operation devices in each cluster based on the acquired plurality of contexts; generating a circuit configuration for each context in which disposition of the operation devices in each cluster and connection of the network modules are made to satisfy the calculated cluster count and operation device count; and outputting the generated circuit configuration.