Patents by Inventor Kiyomitsu Takatani

Kiyomitsu Takatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CMOS output circuit having controlled slope
    Patent number: 5148048
    Abstract: Two p-channel MOS transistors are inserted in series between the positive power supply and the output terminal, whereas two n-channel MOS transistors are inserted in series between the output terminal and the negative power supply. Across the source and drain of one of the p-channel MOS transistors, a first diode is connected in parallel in the forward direction. Similarly, across the source and drain of one of the n-channel MOS transistors, a second diode is connected in parallel in the forward direction.
    Type: Grant
    Filed: June 3, 1991
    Date of Patent: September 15, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Kawasaki, Kiyomitsu Takatani