Patents by Inventor Kiyong Choi

Kiyong Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240080734
    Abstract: Provided are an electronic device and a control method for providing call continuity in a weak electric field environment.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 7, 2024
    Inventors: Juho KIM, Chinkyu KANG, Kiyong LEE, Yongchul CHOI
  • Patent number: 9948239
    Abstract: A method and apparatus are disclosed for a configurable mixer capable of operating in a linear, a legacy, and a low-power mode. In the linear mode, the configurable mixer is configured to operate as a double-balanced mixer to multiply a first differential signal by a second differential signal. In the legacy mode, the configurable mixer is configured to as a double-balanced mixer to multiply a differential signal by a single-ended signal. In the low-power mode, the configurable mixer is configured to operate as a single-balanced mixer to multiply a differential signal by a single-ended signal. The operating mode of the configurable mixer may be based, at least in part, on a mode control signal. In some embodiments, the configurable mixer may be included in an analog front end of a wireless communication device.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 17, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Kiyong Choi, Yi Zeng, Hong Sun Kim, Sasha Vujcic, Chirag Dipak Patel, Aleksandar Miodrag Tasic, Timothy Donald Gathman, Wu-Hsin Chen, Klaas van Zalinge
  • Publication number: 20180083574
    Abstract: A method and apparatus are disclosed for a configurable mixer capable of operating in a linear, a legacy, and a low-power mode. In the linear mode, the configurable mixer is configured to operate as a double-balanced mixer to multiply a first differential signal by a second differential signal. In the legacy mode, the configurable mixer is configured to as a double-balanced mixer to multiply a differential signal by a single-ended signal. In the low-power mode, the configurable mixer is configured to operate as a single-balanced mixer to multiply a differential signal by a single-ended signal. The operating mode of the configurable mixer may be based, at least in part, on a mode control signal. In some embodiments, the configurable mixer may be included in an analog front end of a wireless communication device.
    Type: Application
    Filed: September 21, 2016
    Publication date: March 22, 2018
    Inventors: Kiyong Choi, Yi Zeng, Hong Sun Kim, Sasha Vujcic, Chirag Dipak Patel, Aleksandar Miodrag Tasic, Timothy Donald Gathman, Wu-Hsin Chen, Klaas van Zalinge
  • Patent number: 9350589
    Abstract: Aspects of a wireless apparatus and a method for handling a modulated signal include a frequency generator that produces a clock signal, a first synchronization circuit that generates a first sync enable signal based on an even edge of the clock signal, a second synchronization circuit that generates a second sync enable signal based on an even edge of the clock signal, a first divider having a first initial operating condition that generates a first IQ path based on the first sync enable signal, and a second divider having a second initial operating condition that generates a second IQ path based on the second sync enable signal, wherein the first and second operating conditions are not equal when initially powered.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 24, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Kiyong Choi, Jeongsik Yang, Jin-Su Ko, Yi Zeng
  • Publication number: 20160056987
    Abstract: Aspects of a wireless apparatus and a method for handling a modulated signal include a frequency generator that produces a clock signal, a first synchronization circuit that generates a first sync enable signal based on an even edge of the clock signal, a second synchronization circuit that generates a second sync enable signal based on an even edge of the clock signal, a first divider having a first initial operating condition that generates a first IQ path based on the first sync enable signal, and a second divider having a second initial operating condition that generates a second IQ path based on the second sync enable signal, wherein the first and second operating conditions are not equal when initially powered.
    Type: Application
    Filed: August 21, 2014
    Publication date: February 25, 2016
    Inventors: Kiyong CHOI, Jeongsik YANG, Jin-Su KO, Yi ZENG
  • Patent number: 7221217
    Abstract: A differential RF non-linear power amplifier employing low-voltage transistors in a cascode configuration uses self-biasing solutions rather than external biasing techniques to overcome transistor breakdown problems. The self-biasing solution ensures that the cascode devices and driver device operate below breakdown voltage limitations. A low resistance circuit is placed in parallel with the self-biased circuitry to mitigate increased on-resistance created by the self-biasing solution. PMOS and NMOS inverter legs provide digital programming of the conduction angle for the power amplifier. Changing the PMOS and NMOS strengths in the chain of inverter legs changes the conduction angle.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: May 22, 2007
    Assignee: University of Washington
    Inventors: Kiyong Choi, David J. Allstot
  • Publication number: 20040217813
    Abstract: A differential RF non-linear power amplifier employing low-voltage transistors in a cascode configuration uses self-biasing solutions rather than external biasing techniques to overcome transistor breakdown problems. The self-biasing solution ensures that the cascode devices and driver device operate below breakdown voltage limitations. A low resistance circuit is placed in parallel with the self-biased circuitry to mitigate increased on-resistance created by the self-biasing solution. PMOS and NMOS inverter legs provide digital programming of the conduction angle for the power amplifier. Changing the PMOS and NMOS strengths in the chain of inverter legs changes the conduction angle.
    Type: Application
    Filed: June 19, 2003
    Publication date: November 4, 2004
    Inventors: Kiyong Choi, David J. Allstot