Patents by Inventor Kiyonori Watanabe

Kiyonori Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130313703
    Abstract: A semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. The surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is included on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer is included as having openings exposing part of the conductive pattern. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The thickness of the protective layer, which may function as a package of the semiconductor device, is thus reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.
    Type: Application
    Filed: July 22, 2013
    Publication date: November 28, 2013
    Inventor: Kiyonori Watanabe
  • Patent number: 8274154
    Abstract: A semiconductor device which is capable of preventing interface peeling and a crack from occurring in the vicinity of the edge part of a rewiring layer is provided. The semiconductor device includes a semiconductor substrate, an electrode pad formed on the semiconductor substrate, a first insulation film formed on the semiconductor substrate having a first aperture which exposes the electrode pad, a first conductor film formed on the electrode pad and the first insulation film, an external electrode electrically connected to the first conductor film, and a sealing resin which covers the first conductor film and the first insulation film. The first conductor film includes a plurality of copper layers which are stacked so that an outer edge portion of the first conductor film has a stepped portion.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: September 25, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kiyonori Watanabe
  • Patent number: 8212362
    Abstract: A semiconductor device includes a semiconductor chip having a first main surface having an electrode pad in an exposed state, and an interlayer insulation layer formed on the first main surface so that the electrode pad is partially exposed; a re-wiring layer including a wiring pattern having a linear portion having one end portion electrically connected to the electrode pad and extending from the electrode pad, and a post electrode mounting portion with a recessed polygonal shape and connected to the other end portion of the linear portion; a post electrode formed on the post electrode mounting portion and having a bottom surface with a contour crossing an upper contour of the post electrode mounting portion at more than two points; a sealing portion disposed so that a top of the post electrode is exposed; and an outer terminal formed on the top of the post electrode.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: July 3, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kiyonori Watanabe
  • Patent number: 8110923
    Abstract: An improved manufacturing method of a semiconductor device is provided. The method includes preparing a semiconductor substrate having an integrated circuit together with connection pads. The method also includes forming a dielectric film on the semiconductor substrate. The method also includes forming connection wires having a predetermined pattern on the dielectric film such that the connection wires are electrically connected to the connection pads. The method also includes forming a surface resin layer to partially cover the connection wire. The method also includes forming a metal film over the exposed connection wires. The method also includes forming a display unit having through holes to present identification information in a region corresponding to the center area of the semiconductor substrate on the surface resin layer. The forming of the metal film and the forming of display unit are carried out simultaneously.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: February 7, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kiyonori Watanabe
  • Patent number: 8039310
    Abstract: A semiconductor method comprises a method for making a device comprising: a base; a semiconductor chip provided on the base which includes a first main surface 20a on which a plurality of electrode pads is provided, a surface protecting film provided on the first main surface, a second main surface which opposes the first main surface, and a plurality of side surfaces between the surface of the surface protecting film and the second main surface; an insulating extension portion formed so as to surround the side surfaces of the semiconductor chip; a plurality of wiring patterns electrically connected to the electrode pads, respectively and extended from the electrode pads to the surface of the extension portion; a sealing portion formed on the wiring patterns such that a part of each of the wiring patterns is exposed; and a plurality of external terminals provided on the wiring patterns in a region including the upper side of the extension portion.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: October 18, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kiyonori Watanabe
  • Publication number: 20110089562
    Abstract: A semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. The surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is included on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer is included as having openings exposing part of the conductive pattern. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The thickness of the protective layer, which may function as a package of the semiconductor device, is thus reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.
    Type: Application
    Filed: December 6, 2010
    Publication date: April 21, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Kiyonori Watanabe
  • Publication number: 20110074032
    Abstract: A semiconductor device which is capable of preventing interface peeling and a crack from occurring in the vicinity of the edge part of a rewiring layer is provided. The semiconductor device includes a semiconductor substrate, an electrode pad formed on the semiconductor substrate, a first insulation film formed on the semiconductor substrate having a first aperture which exposes the electrode pad, a first conductor film formed on the electrode pad and the first insulation film, an external electrode electrically connected to the first conductor film, and a sealing resin which covers the first conductor film and the first insulation film. The first conductor film includes a plurality of copper layers which are stacked so that an outer edge portion of the first conductor film has a stepped portion.
    Type: Application
    Filed: December 2, 2010
    Publication date: March 31, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Kiyonori Watanabe
  • Publication number: 20110037147
    Abstract: An improved manufacturing method of a semiconductor device is provided. The method includes preparing a semiconductor substrate having an integrated circuit together with connection pads. The method also includes forming a dielectric film on the semiconductor substrate. The method also includes forming connection wires having a predetermined pattern on the dielectric film such that the connection wires are electrically connected to the connection pads. The method also includes forming a surface resin layer to partially cover the connection wire. The method also includes forming a metal film over the exposed connection wires. The method also includes forming a display unit having through holes to present identification information in a region corresponding to the center area of the semiconductor substrate on the surface resin layer. The forming of the metal film and the forming of display unit are carried out simultaneously.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 17, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Kiyonori Watanabe
  • Patent number: 7884008
    Abstract: A method of forming a semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. This surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is deposited on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer having openings exposing part of the conductive pattern is formed. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The method enables the thickness of the protective layer, which may function as a package of the semiconductor device, to be reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: February 8, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kiyonori Watanabe
  • Patent number: 7879714
    Abstract: There is provide a semiconductor device manufacturing method, including: preparing a substrate; laminating an insulation layer on the substrate; laminating a first underlying metal layer on the insulation layer; forming rewiring on the first underlying metal layer; removing exposed portions of the first underlying metal layer; laminating a second underlying metal layer on the rewiring and the insulation layer; forming a column electrode on the rewiring via the second underlying metal layer; and removing exposed portions of the second underlying metal layer.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: February 1, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kiyonori Watanabe
  • Patent number: 7847407
    Abstract: A semiconductor device which is capable of preventing interface peeling and a crack from occurring in the vicinity of the edge part of a rewiring layer is provided. The semiconductor device comprises a semiconductor substrate; a first interlayer insulation film (a first insulation film) which is formed on the semiconductor substrate, having a first aperture; a first rewiring layer which is formed, ranging from a part of the top surface of the first interlayer insulation film to the inside of the first aperture, and which uppermost surface has a size smaller than the size of the region surrounded by the outer periphery of the surface contacting with the first interlayer insulation film; and a second interlayer insulation film (a second insulation film) which is formed on the first rewiring layer and on the first interlayer insulation film.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: December 7, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kiyonori Watanabe
  • Publication number: 20100283150
    Abstract: The present invention provides a method for forming a semiconductor device, which comprises the steps of preparing a semiconductor wafer including an electrode pad, an insulating film formed with a through hole and a bedding metal layer which are formed in a semiconductor substrate, forming a first resist mask which exposes each area for forming a redistribution wiring, over the bedding metal layer, forming a redistribution wiring connected to the electrode pad and extending in an electrode forming area for a post electrode with the first resist mask as a mask, removing the first resist mask by a dissolving solution to expose each area excluding the electrode forming area for the redistribution wiring and forming a second resist mask disposed with being separated from each side surface of the redistribution wiring, forming a redistribution wiring protective metal film over upper and side surfaces of the exposed redistribution wiring with the second resist mask as a mask, removing the second resist mask by a d
    Type: Application
    Filed: July 15, 2010
    Publication date: November 11, 2010
    Inventor: Kiyonori Watanabe
  • Publication number: 20100221910
    Abstract: A semiconductor device includes a semiconductor substrate having an internal circuit; an electrode pad electrically connected to the internal circuit; an insulating film having a through hole exposing the electrode pad; and a re-distribution wiring pattern formed on the insulating film and electrically connected to the electrode pad. The semiconductor device further includes a recess groove formed in the insulating film around and adjacent to the re-distribution wiring pattern.
    Type: Application
    Filed: May 12, 2010
    Publication date: September 2, 2010
    Inventor: Kiyonori WATANABE
  • Patent number: 7781338
    Abstract: The present invention provides a method for forming a semiconductor device, which comprises the steps of preparing a semiconductor wafer including an electrode pad, an insulating film formed with a through hole and a bedding metal layer which are formed in a semiconductor substrate, forming a first resist mask which exposes each area for forming a redistribution wiring, over the bedding metal layer, forming a redistribution wiring connected to the electrode pad and extending in an electrode forming area for a post electrode with the first resist mask as a mask, removing the first resist mask by a dissolving solution to expose each area excluding the electrode forming area for the redistribution wiring and forming a second resist mask disposed with being separated from each side surface of the redistribution wiring, forming a redistribution wiring protective metal film over upper and side surfaces of the exposed redistribution wiring with the second resist mask as a mask, removing the second resist mask by a d
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: August 24, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kiyonori Watanabe
  • Patent number: 7741705
    Abstract: A semiconductor device includes a semiconductor substrate having an internal circuit; an electrode pad electrically connected to the internal circuit; an insulating film having a through hole exposing the electrode pad; and a re-distribution wiring pattern formed on the insulating film and electrically connected to the electrode pad. The semiconductor device further includes a recess groove formed in the insulating film around and adjacent to the re-distribution wiring pattern.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: June 22, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kiyonori Watanabe
  • Publication number: 20100038779
    Abstract: A semiconductor device includes a semiconductor chip having a first main surface having an electrode pad in an exposed state, and an interlayer insulation layer formed on the first main surface so that the electrode pad is partially exposed; a re-wiring layer including a wiring pattern having a linear portion having one end portion electrically connected to the electrode pad and extending from the electrode pad, and a post electrode mounting portion with a recessed polygonal shape and connected to the other end portion of the linear portion; a post electrode formed on the post electrode mounting portion and having a bottom surface with a contour crossing an upper contour of the post electrode mounting portion at more than two points; a sealing portion disposed so that a top of the post electrode is exposed; and an outer terminal formed on the top of the post electrode.
    Type: Application
    Filed: October 21, 2009
    Publication date: February 18, 2010
    Inventor: Kiyonori WATANABE
  • Patent number: 7626271
    Abstract: A semiconductor device includes a semiconductor chip having a first main surface having an electrode pad in an exposed state, and an interlayer insulation layer formed on the first main surface so that the electrode pad is partially exposed; a re-distribution wiring layer including a wiring pattern having a linear portion having one end portion electrically connected to the electrode pad and extending from the electrode pad, and a post electrode mounting portion with a recessed polygonal shape and connected to the other end portion of the linear portion; a post electrode formed on the post electrode mounting portion and having a bottom surface with a contour crossing an upper contour of the post electrode mounting portion at more than two points; a sealing portion disposed so that a top of the post electrode is exposed; and an outer terminal formed on the top of the post electrode.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: December 1, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kiyonori Watanabe
  • Publication number: 20090258486
    Abstract: A method of forming a semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. This surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is deposited on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer having openings exposing part of the conductive pattern is formed. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The method enables the thickness of the protective layer, which may function as a package of the semiconductor device, to be reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.
    Type: Application
    Filed: June 23, 2009
    Publication date: October 15, 2009
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Kiyonori Watanabe
  • Patent number: 7582972
    Abstract: A semiconductor device includes a semiconductor substrate with circuit elements and electrode pads formed on one surface. This surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is deposited on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer having openings exposing part of the conductive pattern is formed. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. This structure enables the thickness of the protective layer, which may function as a package of the semiconductor device, to be reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: September 1, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kiyonori Watanabe
  • Publication number: 20090215258
    Abstract: There is provide a semiconductor device manufacturing method, including: preparing a substrate; laminating an insulation layer on the substrate; laminating a first underlying metal layer on the insulation layer; forming rewiring on the first underlying metal layer; removing exposed portions of the first underlying metal layer; laminating a second underlying metal layer on the rewiring and the insulation layer; forming a column electrode on the rewiring via the second underlying metal layer; and removing exposed portions of the second underlying metal layer.
    Type: Application
    Filed: January 22, 2009
    Publication date: August 27, 2009
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Kiyonori Watanabe