Patents by Inventor Kiyoshi Asao

Kiyoshi Asao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6557154
    Abstract: A PCB (Printed Circuit Board) design support system and a PCB design method reduce radiation of electromagnetic waves by optimizing layout of a substrate while following a conventional method for designing a PCB and maintaining a conventional structure. The PCB design support system includes an input information section for a ground plane structure, power plane structure and layout of a PCB, a circuit model section for calculating voltages between the ground plane and power plane and distribution of currents flowing on the ground plane and power plane using input information, a frequency selection section and a section to display obtained voltage and current distribution in a form of two-dimensional voltage and current distribution maps corresponding to shapes of the PCB. The PCB design support system enables a via-hole disposed between planes and/or wiring installed between planes causing variations in voltages to be specified in a precautionary manner from a PCB design stage.
    Type: Grant
    Filed: November 24, 2000
    Date of Patent: April 29, 2003
    Assignee: NEC Corporation
    Inventors: Takashi Harada, Hideki Sasaki, Eiji Hankui, Kiyoshi Asao
  • Patent number: 6519741
    Abstract: Disclosed is a power decoupling circuit generating system and method capable of easily generating a power decoupling circuit for each device such as an LSI. On the basis of information regarding parameters of generating a power decoupling circuit held in a capacitor parts library and a line calculation parameter file, a power decoupling circuit of a &pgr;-type low pass filter construction having first and second decoupling capacitors to be added to a power supply terminal of a device as a target from which high frequency noise is prevented from being passed to a power plane and a power line corresponding to an inductance is automatically generated by a power decoupling circuit generating unit, thereby making calculation for generating the power decoupling circuit unnecessary.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: February 11, 2003
    Assignee: NEC Corporation
    Inventors: Takahiro Yaguchi, Kiyoshi Asao, Hideki Sasaki, Takashi Harada
  • Publication number: 20010010035
    Abstract: Disclosed is a power decoupling circuit generating system and method capable of easily generating a power decoupling circuit for each device such as an LSI. On the basis of information regarding parameters of generating a power decoupling circuit held in a capacitor parts library and a line calculation parameter file, a power decoupling circuit of a &pgr;-type low pass filter construction having first and second decoupling capacitors to be added to a power supply terminal of a device as a target from which high frequency noise is prevented from being passed to a power plane and a power line corresponding to an inductance is automatically generated by a power decoupling circuit generating unit, thereby making calculation for generating the power decoupling circuit unnecessary.
    Type: Application
    Filed: January 19, 2001
    Publication date: July 26, 2001
    Applicant: NEC CORPORATION
    Inventors: Takahiro Yaguchi, Kiyoshi Asao, Hideki Sasaki, Takashi Harada