Patents by Inventor Kiyoshi Demizu

Kiyoshi Demizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7411274
    Abstract: The present invention has been made in order to manufacture a silicon semiconductor substrate used for a semiconductor integrated circuit device, higher in carrier mobility, especially in electron mobility, which is a carrier of an n-type FET, on a {100} plane as a main surface, and provides a silicon semiconductor substrate and a method for manufacturing the same, wherein the conventional RCA cleaning is employed without the use of special cleaning and the surface of the substrate is planarized at an atomic level to thereby decrease the surface roughness thereof without the use of the radical oxidation. The present invention provides a silicon semiconductor substrate comprising: a {110} plane or a plane inclined from a {110} plane as a main surface of the substrate; and steps arranged at an atomic level along a <110> orientation on the main surface.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: August 12, 2008
    Assignees: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hideki Yamanaka, Kiyoshi Demizu, Tadahiro Ohmi, Akinobu Teramoto, Shigetoshi Sugawa
  • Patent number: 7315064
    Abstract: The present invention provides a bonded wafer, wherein at least a silicon single crystal layer is formed on a silicon single crystal wafer, the silicon single crystal layer has a crystal plane orientation of {110}, and the silicon single crystal wafer has a crystal plane orientation of {100}. The present invention also provides a method of producing a bonded wafer, wherein after at least a first silicon single crystal wafer having a crystal plane orientation of {110} and a second silicon single crystal wafer having a crystal plane orientation of {100} are bonded directly or bonded via an insulator film, the first silicon single crystal wafer is made into a thin film. Thereby, there can be provided a wafer possible to obtain a MIS device having good characteristics by utilizing a silicon single crystal wafer having the {110} plane.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: January 1, 2008
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kiyoshi Mitani, Kiyoshi Demizu, Isao Yokokawa, Tadahiro Ohmi, Shigetoshi Sugawa
  • Publication number: 20060131553
    Abstract: The present invention has been made in order to manufacture a silicon semiconductor substrate used for a semiconductor integrated circuit device, higher in carrier mobility, especially in electron mobility, which is a carrier of an n-type FET, on a {100} plane as a main surface, and provides a silicon semiconductor substrate and a method for manufacturing the same, wherein the conventional RCA cleaning is employed without the use of special cleaning and the surface of the substrate is planarized at an atomic level to thereby decrease the surface roughness thereof without the use of the radical oxidation. The present invention provides a silicon semiconductor substrate comprising: a {110} plane or a plane inclined from a {110} plane as a main surface of the substrate; and steps arranged at an atomic level along a <110> orientation on the main surface.
    Type: Application
    Filed: January 29, 2004
    Publication date: June 22, 2006
    Inventors: Hideki Yamanaka, Kiyoshi Demizu, Tadahiro Ohmi, Akinobu Teramoto, Shigetoshi Sugawa
  • Patent number: 7052974
    Abstract: The present invention provides a bonded wafer, wherein at least a silicon single crystal layer is formed on a silicon single crystal wafer, the silicon single crystal layer has a crystal plane orientation of {110}, and the silicon single crystal wafer has a crystal plane orientation of {100}. The present invention also provides a method of producing a bonded wafer, wherein after at least a first silicon single crystal wafer having a crystal plane orientation of {110} and a second silicon single crystal wafer having a crystal plane orientation of {100} are bonded directly or bonded via an insulator film, the first silicon single crystal wafer is made into a thin film. Thereby, there can be provided a wafer possible to obtain a MIS device having good characteristics by utilizing a silicon single crystal wafer having the {110} plane.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: May 30, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kiyoshi Mitani, Kiyoshi Demizu, Isao Yokokawa, Tadahiro Ohmi, Shigetoshi Sugawa
  • Publication number: 20060099791
    Abstract: The present invention provides a bonded wafer, wherein at least a silicon single crystal layer is formed on a silicon single crystal wafer, the silicon single crystal layer has a crystal plane orientation of {110}, and the silicon single crystal wafer has a crystal plane orientation of {100}. The present invention also provides a method of producing a bonded wafer, wherein after at least a first silicon single crystal wafer having a crystal plane orientation of {110} and a second silicon single crystal wafer having a crystal plane orientation of {100} are bonded directly or bonded via an insulator film, the first silicon single crystal wafer is made into a thin film. Thereby, there can be provided a wafer possible to obtain a MIS device having good characteristics by utilizing a silicon single crystal wafer having the {110} plane.
    Type: Application
    Filed: December 15, 2005
    Publication date: May 11, 2006
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kiyoshi Mitani, Kiyoshi Demizu, Isao Yokokawa, Tadahiro Ohmi, Shigetoshi Sugawa
  • Publication number: 20050003648
    Abstract: The present invention provides a bonded wafer, wherein at least a silicon single crystal layer is formed on a silicon single crystal wafer, the silicon single crystal layer has a crystal plane orientation of {110}, and the silicon single crystal wafer has a crystal plane orientation of {100}. The present invention also provides a method of producing a bonded wafer, wherein after at least a first silicon single crystal wafer having a crystal plane orientation of {110} and a second silicon single crystal wafer having a crystal plane orientation of {100} are bonded directly or bonded via an insulator film, the first silicon single crystal wafer is made into a thin film. Thereby, there can be provided a wafer possible to obtain a MIS device having good characteristics by utilizing a silicon single crystal wafer having the {110} plane.
    Type: Application
    Filed: November 25, 2002
    Publication date: January 6, 2005
    Inventors: Kiyoshi Mitani, Kiyoshi Demizu, Isao Yokokawa, Tadahiro Ohmi, Shigetoshi Sugawa
  • Patent number: 6787797
    Abstract: In order to improve the productivity or production yield of chips in the process for device fabrication, the present invention provides a wafer or an apparatus of process for fabricating semiconductor devices having the backside of the wafer or the surface of a wafer holding means adjusted so as to have a distribution in contact surface density between the surface of the wafer holding means and the backside of the wafer when the semiconductor wafer is held on the wafer holding means in the process for fabricating devices.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: September 7, 2004
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kiyoshi Demizu, Tadahiro Kato, Shigeyoshi Netsu
  • Publication number: 20020167006
    Abstract: In order to improve the productivity or production yield of chips in the process for device fabrication, the present invention provides a wafer or an apparatus of process for fabricating semiconductor devices having the backside of the wafer or the surface of a wafer holding means adjusted so as to have a distribution in contact surface density between the surface of the wafer holding means and the backside of the wafer when the semiconductor wafer is held on the wafer holding means in the process for fabricating devices.
    Type: Application
    Filed: April 22, 2002
    Publication date: November 14, 2002
    Inventors: Kiyoshi Demizu, Tadahiro Kato, Shigeyoshi Netsu
  • Patent number: 6131052
    Abstract: A semiconductor manufacturing system capable of reducing time required for manufacture of semiconductors with effective use of waiting time of lots in storage equipment is provided. While a lot including a plurality of semiconductor wafers are stored in storage equipment, the semiconductor wafers in the lot are subjected to non-processing steps carried out by non-processing apparatuses such as measuring apparatuses, inspecting apparatuses, and contaminant removing apparatuses.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: October 10, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Cozy Ban, Kiyoshi Demizu