Abstract: A writeable control store in a data processing system is provided with a dual mode capability. Coupled with the control store in the system is a central processing unit which may provide the next address of the control store's memory dependent upon the mode of the control store. Otherwise, also dependent upon such mode, the control store memory is addressed, dependent upon the results of tests conducted in the central processing unit, by one of at least two alternative addresses. The control words addressed in the writeable control store are used to control the operation of the central processing unit.

Abstract: A control store coupled with a central processing unit to transfer information over a common electrical bus and coupled to transfer information over a private interface between the control store and unit. The control store includes firmware words for providing additional control of the unit, which also has a control memory for controlling the operation of the unit. The private interface is used to transfer addressed firmware words from the control store to the unit for use by the unit including generating the next address to be used by the control store, which next address is also provided from the unit to the control store over the private interface. Such private interface is also used to transfer the results of one or more tests performed by the unit, which results indicate which of at least two alternative addresses are to be used by the control store.

Abstract: A data processing unit's request to a data processing device for the transfer of control and processing of an operation in response to an instruction from the unit, is stalled by the device, dependent on the type of instruction, for a period of time, also dependent on the type of instruction, until the device is ready to process such operation. A shift register arrangement is used in the device, which, dependent on the indicia stored therein, which indicia are appropriately loaded in such register dependent on the type of instruction, is used to delay a response to the unit by requesting the unit to make another request to the device to process the operation called for by the instruction.