Patents by Inventor Kiyoshi Hisano

Kiyoshi Hisano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5606684
    Abstract: A buffer memory capable of storing contents of a plurality of tracks of a disk volume is provided in a disk controller or a disk drive, and in dump processing requested by a higher rank unit (CPU) to the disk controller, the data is immediately transferred from the buffer memory if the data to be dumped is present in the buffer memory, and if the data to be dumped is not present in the buffer memory, dump prefetching into the buffer memory is started and the execution of the dump processing is interrupted so that an on-line input/output operation other than the dump processing is accepted. When the dump prefetching into the buffer memory is over, the interrupted dump processing is resumed.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: February 25, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Nakano, Masafumi Nozawa, Kiyoshi Hisano, Akihito Ogino, Akira Kurano, Hiroyuki Kitajima, Akihiko Togawa
  • Patent number: 5410666
    Abstract: A buffer memory capable of storing contents of a plurality of tracks of a disk volume is provided in a disk controller or a disk drive, and in dump processing requested by a higher rank unit (CPU) to the disk controller, the data is immediately transferred from the buffer memory if the data to be dumped is present in the buffer memory, and if the data to be dumped is not present in the buffer memory, dump prefetching into the buffer memory is started and the execution of the dump processing is interrupted so that an on-line input/output operation other than the dump processing is accepted. When the dump prefetching into the buffer memory is over, the interrupted dump processing is resumed.
    Type: Grant
    Filed: September 17, 1990
    Date of Patent: April 25, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Nakano, Masafumi Nozawa, Kiyoshi Hisano, Akihito Ogino, Akira Kurano, Hiroyuki Kitajima, Akihiko Togawa
  • Patent number: 5335327
    Abstract: A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, accesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: August 2, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoshi Hisano, Ken Hirashima, Hiroyuki Kurosawa, Kenji Kubota, Shuji Sugimoto
  • Patent number: 5267097
    Abstract: When a positioning operation of a head on a track of a disk including a target record is completed, information is read out from the track of the disk and stored in a buffer memory without waiting a read command from a host side controller. A transfer operation of the target record of the information from the buffer memory to the controller is performed when the controller is not busy and generates the read command. A transfer rate of the record from the buffer memory to the controller is made faster than a read rate of the information from a disk or a write rate into the buffer memory, so that a nominal transfer rate of an entire system is increased without changing the read or write rate.
    Type: Grant
    Filed: September 14, 1992
    Date of Patent: November 30, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Akihito Ogino, Michio Miyazaki, Kiyoshi Hisano
  • Patent number: 5241640
    Abstract: A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, acesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes.
    Type: Grant
    Filed: October 10, 1989
    Date of Patent: August 31, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoshi Hisano, Ken Hirashima, Hiroyuki Kurosawa, Kenji Kubota, Shuji Sugimoto
  • Patent number: 5226157
    Abstract: In a data processing system having a first external memory, a second external memory, and a control memory for storing information on data renewals in the first external memory, a system and a method provide for back-up operations in parallel with ordinary data processing, including dump processing in which renewed data parts in the first external memory are copied as backup data into the second external memory with reference to the contents of the control memory.
    Type: Grant
    Filed: March 2, 1989
    Date of Patent: July 6, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Nakano, Masafumi Nozawa, Akira Kurano, Kiyoshi Hisano, Masayuki Hoshino
  • Patent number: 4870565
    Abstract: A computer system having a disk cache unit between a disk unit and the main storage unit. Ordinarily, the data transfer processing is carried out between the disk unit and the disk cache unit and between the disk cache unit and the main storage unit in this case. The present invention is characterized by enabling these two data transfer operations to be executed in parallel and to prevent a director from becoming the bottleneck of the processing due to the concentrated processing requests. For this purpose, the present invention provides for conducting a data transfer between the disk cache unit and a disk unit while a data transfer is taking place between the main storage unit and the disk cache unit. The director is configured, for example, with two data transfer controlling systems and two data transfer units for carrying out data transfer according to instructions for the two data transfer controlling systems.
    Type: Grant
    Filed: March 13, 1989
    Date of Patent: September 26, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Toru Nishigaki, Akira Kurano, Kiyoshi Hisano, Yoshiro Shiroyana
  • Patent number: 4800483
    Abstract: The present invention relates to a computer system having a disk cache unit between a disk unit and the main storage unit. Ordinarily, the data transfer processing is carried out between the disk unit and the disk cache unit and between the disk cache unit and the main storage unit in this case under control of a director. The present invention is characterized by enabling these two data transfer operations to be executed in parallel and to prevent the director from becoming the bottleneck of the processing due to the concentrated processing requests. For this purpose, the present invention provides for a data transfer between the disk cache unit and a disk unit while a data transfer is taking place between the main storage unit and the disk cache unit.
    Type: Grant
    Filed: May 28, 1987
    Date of Patent: January 24, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Toru Nishigaki, Akira Kurano, Kiyoshi Hisano, Yoshiro Shiroyanagi