Patents by Inventor Kiyoshi Hyodo

Kiyoshi Hyodo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8736064
    Abstract: An interconnect element is provided. A monolithic dielectric element has a first exposed major surface, a plurality of first recesses extending inwardly from the first major surface, and a second exposed major surface remote from the first major surface, a plurality of second recesses extending inwardly from the second major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses and extend in one or more directions along the first major surface. A plurality of second metal interconnect patterns are embedded in the plurality of second recesses and extend in one or more directions along the second major surface. A plurality of non-hollow metal posts extend through the dielectric element between at least some of the plurality of first metal interconnect patterns and at least some of the plurality of second metal interconnect patterns.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: May 27, 2014
    Assignee: Invensas Corporation
    Inventors: Hideki Kotake, Kiyoshi Hyodo, Inetaro Kurosawa, Yukio Hashimoto, Toku Yoshino, Tomoo Iijima
  • Publication number: 20110057324
    Abstract: An interconnect element is provided. A monolithic dielectric element has a first exposed major surface, a plurality of first recesses extending inwardly from the first major surface, and a second exposed major surface remote from the first major surface, a plurality of second recesses extending inwardly from the second major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses and extend in one or more directions along the first major surface. A plurality of second metal interconnect patterns are embedded in the plurality of second recesses and extend in one or more directions along the second major surface. A plurality of non-hollow metal posts extend through the dielectric element between at least some of the plurality of first metal interconnect patterns and at least some of the plurality of second metal interconnect patterns.
    Type: Application
    Filed: November 8, 2010
    Publication date: March 10, 2011
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Hideki Kotake, Kiyoshi Hyodo, Inetaro Kurosawa, Yukio Hashimoto, Toku Yoshino, Tomoo Iijima
  • Publication number: 20080169568
    Abstract: A multilayer interconnect element is provided which includes at least one dielectric element in which metal interconnect patterns are exposed at an outer surface thereof, the metal interconnect patterns having outer surfaces which are co-planar with an exposed outer surface of the dielectric element. In addition, multilayer interconnect elements are provided in which second interconnect elements which do not have co-planar interconnect patterns are integrated therewith as intermediate elements, and the resulting multilayer interconnect element has co-planar interconnect patterns.
    Type: Application
    Filed: August 29, 2007
    Publication date: July 17, 2008
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Hideki Kotake, Kiyoshi Hyodo, Inetaro Kurosawa, Yukio Hashimoto, Toku Yoshino, Tomoo Iijima
  • Publication number: 20080136041
    Abstract: An interconnect element is provided which includes a dielectric element having a major surface. Metal interconnect patterns are embedded in recesses which extend inwardly from the major surface, the outer surfaces of the interconnect patterns being substantially co-planar with the major surface and extending in one or more directions of the major surface. A projecting conductive film extends over the major surface in at least one direction parallel to a plane defined by the major surface such that it contacts the dielectric element along at least a portion of the major surface and conductively contacts an outer surface of at least one of the metal interconnect patterns.
    Type: Application
    Filed: May 23, 2007
    Publication date: June 12, 2008
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Hideki Kotake, Kiyoshi Hyodo, Inetaro Kurosawa, Yukio Hashimoto, Toku Yoshino, Tomoo Iijima
  • Publication number: 20070221329
    Abstract: An apparatus and method are provided for processing an item by distributing a liquid onto a surface of the item. The apparatus includes a conveyor which defines an undulating path which varies in vertical position relative to the direction of movement of the item conveyable along the path. Thus, the path has at least one apex at a location of the path higher than other locations in the direction of movement along the path. A sprayer is operable to spray the liquid onto the surface of the item at a location that is substantially aligned to the apex of the path.
    Type: Application
    Filed: October 23, 2006
    Publication date: September 27, 2007
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Kazuo Sakuma, Inetaro Kurosawa, Kiyoshi Hyodo
  • Patent number: 6917848
    Abstract: A manufacturing system for printed wiring boards divides printed wiring boards scheduled to be manufactured into non-fractional and fractional groups depending on the content of an order remainder list. The printed wiring boards categorized as non-fractional are panelized having the same shapes while the printed wiring boards categorized as fractional are grouped corresponding to manufacturing conditions thereof. Then, each group of the printed wiring boards are panelized with different shapes in a predetermined manufacturing block. Consequently, the generation of incidental products or the waste of material can be prevented.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: July 12, 2005
    Assignee: Fujitsu Limited
    Inventors: Akitaka Nakayama, Akio Ikeda, Kiyoshi Hyodo, Kazuo Uchida
  • Patent number: 6893576
    Abstract: This invention is a method of manufacturing a multi-layer printed wiring board including an internal layer circuit forming step, a outer layer circuit forming step, and a solder resist forming step. In the solder resist forming step, the surface of a board subjected to the outer layer circuit forming step is coated with a photosensitive solder resist material, the solder resist material is coated with a photosensitive film; a light shielding mask is formed by irradiating a laser beam on the photosensitive film according to a formed pattern of the solder resist, the solder resist material is exposed by using the light shielding mask, the light shielding mask is removed, and the solder resist material which is not exposed is removed.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: May 17, 2005
    Assignee: Fujitsu Limited
    Inventors: Akitaka Nakayama, Akio Ikeda, Kiyoshi Hyodo, Kazuo Uchida