Patents by Inventor Kiyoshi Iyogi
Kiyoshi Iyogi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6426154Abstract: The present invention provides a ceramic circuit board comprising: a ceramic substrate and a metal circuit plate bonded to the ceramic substrate through a brazing material layer; wherein the brazing material layer is composed of Al—Si group brazing material and an amount of Si contained in the brazing material is 7 wt % or less. In addition, it is preferable to form a thinned portion, holes, or grooves to outer peripheral portion of the metal circuit plate. According to the above structure of the present invention, there can be provided a ceramic circuit board having both high bonding strength and high heat-cycle resistance, and capable of increasing an operating reliability as electronic device.Type: GrantFiled: September 25, 2000Date of Patent: July 30, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Naba, Hiroshi Komorita, Noritaka Nakayama, Kiyoshi Iyogi
-
Patent number: 5907187Abstract: In such electronic components as semiconductor packages and semiconductor chips which are possessed of groups of connecting bumps as input and output terminals, the groups of connecting bumps comprise not less than two kinds of connecting bumps different in melting point or not less than two kinds of connecting bumps different in mechanical strength. The groups of connecting bumps comprise connecting bumps made of high temperature solder or connecting bumps made of a high strength In type solder in the part of formation thereof. The connecting bumps made of high temperature solder are not directly affected by the influence of displacement because they retain the shape of a ball even after the step of connection such as solder reflow. The connecting bumps made of In type solder form connecting parts of high strength. These groups of connecting bumps contribute to exalt the reliability of the connecting parts without decreasing the number of input and output terminals.Type: GrantFiled: July 14, 1995Date of Patent: May 25, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Kaoru Koiwa, Koji Yamakawa, Kiyoshi Iyogi, Takaaki Yasumoto, Nobuo Iwase
-
Patent number: 5736790Abstract: Disclosed is a bump formed on a pad which is provided on either a semiconductor chip or a package or a wiring substrate for input or output thereof, for making electric connection on the pad. The bump has: a projection projecting from the pad; a ball having conductivity and located above the pad; and a conductive bonding material for bonding the pad for and the ball, wherein creep strength of the ball is larger than strength of the conductive bonding material. With another conductive bonding material provided on the other pad of a wiring substrate or a package, the ball of the bump of the semiconductor chip or the package is placed close to another pad of the wiring substrate or package. The conductive bonding material of the other pad is heated and melted to connect the ball and the other pad of the wiring substrate or package by the conductive bonding material.Type: GrantFiled: September 20, 1996Date of Patent: April 7, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Iyogi, Kaoru Koiwa, Keiichi Yano, Hironori Asai
-
Patent number: 5714801Abstract: A semiconductor package is disclosed which is provided with a multilayer ceramic substrate such as, for example, a multilayer aluminum nitride substrate having a surface for mounting a semiconductor device and, at the same time, having an inner wiring layer electrically connected to the semiconductor device. On the surface of the multilayer ceramic substrate for forming terminals thereon, input and output terminals such as, for example, pin terminals and bump terminals electrically connected to the inner wiring layer. The input and output terminals embrace signal terminals, ground terminals, and power source terminals. The signal terminals among other terminals are so disposed that they may be each positioned adjacently to at least one ground terminal or power source terminal. This semiconductor package possesses perfect transmission properties even for signals of such a high frequency as exceeds the order of GHz. The dispersion of the transmission properties is small.Type: GrantFiled: March 29, 1996Date of Patent: February 3, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Keiichi Yano, Jun-ichi Kudo, Koji Yamakawa, Kiyoshi Iyogi
-
Patent number: 5622769Abstract: According to this invention, there is disclosed a thermal conductivity substrate which includes an aluminum nitride sintered body and a coating layer formed on the body of aluminum phosphate and having a surface roughness of 1 .mu.m or less, and which has excellent humidity resistance and chemical resistance.Type: GrantFiled: February 10, 1994Date of Patent: April 22, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Kozuka, Masaru Hayashi, Katsuyoshi Oh-Ishi, Takaaki Yasumoto, Nobuo Iwase, Hiroshi Endo, Koji Yamakawa, Kaoru Koiwa, Kiyoshi Iyogi
-
Patent number: 5412160Abstract: A circuit board comprising a substrate, at least one dielectric film formed on the substrate and made of at least one selected from the group consisting of AlN, BN, diamond, diamond-like carbon, BeO and SiC, the dielectric film having pores of a porosity of 5 to 95% by volume, and at least one wiring metal film formed on the dielectric film.Type: GrantFiled: March 15, 1994Date of Patent: May 2, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Takaaki Yasumoto, Nobuo Iwase, Kaoru Koiwa, Koji Yamakawa, Kiyoshi Iyogi
-
Patent number: 5326623Abstract: A circuit board including a circuit pattern adhered firmly to a ceramic substrate and capable of eliminating an increase in resistivity due to an influence of an external environment, particularly, a thermal influence is disclosed. The circuit board comprises a ceramic substrate, and a circuit pattern formed on the substrate and having a multilayered structure in which a bonding layer comprising Ti and at least one element selected from the group consisting of N and O, a conductor layer consisting essentially of Cu, and a protective layer comprising Ti and at least one element selected from the group consisting of N and O are stacked in the order named.Type: GrantFiled: January 28, 1993Date of Patent: July 5, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Koji Yamakawa, Kaoru Koiwa, Takaaki Yasumoto, Kiyoshi Iyogi, Nobuo Iwase
-
Patent number: 5041700Abstract: A circuit board includes an aluminum nitride substrate, and a circuit pattern formed on the substrate and having a multilayered structure in which a metal oxynitride layer represented by formula Al.sub.u Ml.sub.v M2.sub.x O.sub.y N.sub.z (wherein M1 represents a metal selected from the group consisting of Ti, Cr, Ta, and Zr, M2 represents a metal selected from the group consisting of Ni, Pt, Pd, W, Nb, and Mo, u represents 3 to 50 atm %, v represents 3 to 78 atm %, x represents 0 to 50 atm %, y represents 0.005 to 25 atm %, and z represents 5 to 70 atm %), a bonding layer consisting essentially of a metal represented by M1, a barrier layer consisting essentially of a metal represented by M2, and a conductor layer consisting essentially of Au are stacked in the order named.Type: GrantFiled: September 27, 1990Date of Patent: August 20, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Iyogi, Takaaki Yasumoto, Toshirou Yanazawa, Nobuo Iwase
-
Patent number: 5019187Abstract: According to the present invention, there is provided an electronic component part comprising (i) a high thermal conductivity ceramic circuit board, (ii) terminal pins located over said circuit board, and (iii) a metal brazing material having metal brazing powder, at least one element selected from the Group IVa elements and a metal having a melting point higher than that of the metal brazing powder, the metal brazing material bonding said board and said pins. According to the present invention, metal, such as input/output terminal pins can very firmly be bonded to ceramic, such as a circuit board, within an atmosphere of, for example, N.sub.2 gas without the scattering of any brazing material in which case, unlike the prior art method, any vacuum furnace is not employed.Type: GrantFiled: March 7, 1990Date of Patent: May 28, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Iyogi, Masako Nakahashi, Hiromitsu Takeda, Makoto Shirokane
-
Patent number: 4924033Abstract: According to the present invention, there is provided an electronic component part comprising (i) a high thermal conductivity ceramic circuit board, (ii) terminal pins located over said circuit board, and (iii) a metal brazing material having metal brazing powder, at least one element selected from the Group IVa elements and a metal having a melting point higher than that of the metal brazing powder, the metal brazing material bonding said board and said pins. According to the present invention, metal, such as input/output terminal pins can very firmly be bonded to ceramic, such as a circuit board, within an atmosphere of, for example, N.sub.2 gas without the scattering of any brazing material in which case, unlike the prior art method, vacuum furnace is not employed.Type: GrantFiled: March 3, 1989Date of Patent: May 8, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Iyogi, Masako Nakahashi, Hiromitsu Takeda, Makoto Shirokane
-
Patent number: 4919731Abstract: The present invention provides an electronic component part with terminal pins very closely and very strongly bonded to a high thermal conductivity ceramics circuit board and a method for simply and continuously manufacturing electronic component parts, with a high operability, each with terminal pins bonded to a high thermal conductivity ceramics circuit board. According to the present invention, an electronic component part is provided in which terminal pins are bonded to a high thermal conductivity ceramics circuit board by a brazing metal, containing at least one kind of Group IVa elements.Type: GrantFiled: February 10, 1989Date of Patent: April 24, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Iyogi, Takaaki Yasumoto, Toshirou Yanazawa, Nobuo Iwase, Masako Nakahashi, Hiromitsu Takeda
-
Patent number: 4855251Abstract: According to the present invention, a method is provided of manufacturing electronic parts, comprising a first step of forming on the surface of a substrate a bump wherein the metal particles of that portion of the bump which contacts the surface of the substrate have a larger diameter than the metal particles of that portion of the bump which does not contact the surface of the substrate, a second step of transferring the bump to an electrode lead, and a third step of connecting an electrode lead to a predetermined electrode section of the semiconductor chip, by means of the transferred bump. The method of the present invention ensures that the bump does not fall off during the electroplating and washing steps, and ensures a high-strength bond between the transferred bump and the electrode section of a semiconductor chip.Type: GrantFiled: November 3, 1988Date of Patent: August 8, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Iyogi, Koji Yamakawa, Nobuo Iwase
-
Patent number: 4835344Abstract: The present invention provides an electronic component part with terminal pins very closely and very strongly bonded to a high thermal conductivity ceramics circuit board and a method for simply and continuously manufacturing electronic component parts, with a high operability, each with terminal pins bonded to a high thermal conductivity ceramics circuit board. According to the present invention, an electronic component part is provided in which terminal pins are bonded to a high thermal conductivity ceramics circuit board by a brazing metal, containing at least one kind of Group IVa elements.Type: GrantFiled: February 10, 1988Date of Patent: May 30, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Iyogi, Takaaki Yasumoto, Toshirou Yanazawa, Nobuo Iwase, Masako Nakahashi, Hiromitsu Takeda
-
Patent number: 4659611Abstract: A high thermal conductivity circuit substrate is provided comprising a sintered aluminum nitride ceramic substrate consisting essentially of one member selected from the group of yttrium, the rare earth metals and the alkali earth metals and an electrically conductive thick film paste for a conductive layer formed on the substrate.Type: GrantFiled: February 27, 1985Date of Patent: April 21, 1987Assignee: Kabushiki Kaisha ToshibaInventors: Nobuo Iwase, Kazuo Anzai, Kazuo Shinozaki, Akihiko Tsuge, Kazutaka Saitoh, Kiyoshi Iyogi, Noboru Sato, Mitsuo Kasori