Patents by Inventor Kiyoshi Kato

Kiyoshi Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE
    Publication number: 20160260718
    Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.
    Type: Application
    Filed: May 18, 2016
    Publication date: September 8, 2016
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Kiyoshi KATO
  • Semiconductor device with antenna and light-emitting element
    Patent number: 9437777
    Abstract: When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: September 6, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tamae Takano, Nobuharu Ohsawa, Kiyoshi Kato
  • MEMORY DEVICE
    Publication number: 20160247548
    Abstract: To provide a memory device where multiple pieces of multilevel data can be written and read. The memory device includes first to fifth transistors, first to fourth capacitors, first to fourth nodes, and first and second wirings. The first node is connected to the first capacitor and a gate of the first transistor, the second node is connected to the second capacitor and a gate of the second transistor, the third node is connected to the third capacitor and a gate of the third transistor, and the fourth node is connected to the fourth capacitor and a gate of the fourth transistor. Multiple pieces of multilevel data is written to the first to fourth nodes through the second to fifth transistors. The second to fifth transistors each preferably include an oxide semiconductor in a channel formation region.
    Type: Application
    Filed: February 11, 2016
    Publication date: August 25, 2016
    Inventors: Shunpei YAMAZAKI, Kiyoshi KATO, Takanori MATSUZAKI
  • Semiconductor device and driving method thereof
    Patent number: 9424890
    Abstract: A semiconductor device capable of inhibiting incorrect data readout is provided. In a memory cell including a first transistor, a second transistor, and a third transistor, the potential of a fourth wiring is set to GND when data is written, and the potential is set to VDD when data is read out, for example. Note that the potential of a third wiring is set to GND when data is written and when data is read out, for example. When data is read out, the first transistor is off, so that a first capacitor and a fourth capacitor are connected in series. The potential of a second electrode of the second capacitor increases in this state, and thus part of charges accumulated in the second capacitor transfers to the first capacitor, so that the potential of a node increases.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 23, 2016
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Hiroki Inoue, Kiyoshi Kato, Takanori Matsuzaki
  • Microcontroller capable of being in three modes
    Patent number: 9423860
    Abstract: To provide a microcontroller that can operate in a low power consumption mode. The microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register of the peripheral circuit is formed at an interface with a bus line. A power gate is provided for control of power supply, and the microcontroller can operate in the low power consumption mode where some circuits alone are active, in addition to in a normal operation mode where all circuits are active. A register with no power supply in the low power consumption mode, such as a register of the CPU, includes a volatile memory and a nonvolatile memory.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: August 23, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuji Nishijima, Hidetomo Kobayashi, Tomoaki Atsumi, Kiyoshi Kato
  • Wireless processor, wireless memory, information system, and semiconductor device
    Patent number: 9425215
    Abstract: The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: August 23, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato, Jun Koyama, Yutaka Shionoiri
  • INFORMATION PROCESSING APPARATUS AND ANALYSIS METHOD
    Publication number: 20160231738
    Abstract: Even when there is a large time lag between metrics of a target system, a decrease in analysis accuracy of the target system is prevented. An analysis apparatus (100) includes a processing unit (140) and pre-processing unit (130). The processing unit (140) performs comparative analysis of values of a first metric and a second metric in a system to be analyzed. The pre-processing unit (130) identifies, with respect to the comparative analysis of the first metric and the second metric, a temporal correspondence relation between respective pieces of data used as the first metric and the second metric.
    Type: Application
    Filed: September 11, 2014
    Publication date: August 11, 2016
    Applicant: NEC Corporation
    Inventor: Kiyoshi KATO
  • Semiconductor device and method for manufacturing the same
    Patent number: 9412060
    Abstract: A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 ?/cm2 is formed on at least one surface of each structure body.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: August 9, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato, Takaaki Koen, Yuto Yakubo, Makoto Yanagisawa, Hisashi Ohtani, Eiji Sugiyama, Nozomi Horikoshi
  • Semiconductor device
    Patent number: 9412739
    Abstract: A semiconductor with reduced area is provided. A first transistor includes a first conductor, a first insulator over the first conductor, an oxide semiconductor provided over the first insulator so as to overlap with the first conductor, a second insulator over the oxide semiconductor, a second conductor over the second insulator, and a third conductor and a fourth conductor in contact with the oxide semiconductor. The oxide semiconductor includes a region overlapping with the first region and not overlapping with the second region, and a region not overlapping with the first conductor and overlapping with the second conductor in a region positioned between the third conductor and the fourth conductor when viewed from above. The second transistor is a p-channel transistor. A layer in which the first transistor is provided and a layer in which the second transistor is provided are stacked together.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: August 9, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • NONVOLATILE LATCH CIRCUIT AND LOGIC CIRCUIT, AND SEMICONDUCTOR DEVICE USING THE SAME
    Publication number: 20160226471
    Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.
    Type: Application
    Filed: April 14, 2016
    Publication date: August 4, 2016
    Inventors: Kiyoshi KATO, Jun KOYAMA
  • SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE
    Publication number: 20160217848
    Abstract: To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including an SRAM capable of backing up data to the nonvolatile memory and a peripheral circuit of the memory cell are configured to offer different power gating states. In a first period, which is extremely short, the bit line is brought into an electrically floating state by turning off the switch. In a second period, which is longer than the first period, power gating is performed on the memory cell. In a third period, which is longer than the second period, power gating is performed on the memory cell and the peripheral circuits.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 28, 2016
    Inventors: Takahiko ISHIZU, Wataru UESUGI, Kiyoshi KATO, Tatsuya ONUKI
  • METHOD FOR DRIVING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    Publication number: 20160203871
    Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.
    Type: Application
    Filed: January 8, 2016
    Publication date: July 14, 2016
    Inventors: Shuhei Nagatsuka, Hiroki Inoue, Takahiko Ishizu, Takanori Matsuzaki, Yutaka Shionoiri, Kiyoshi Kato
  • Semiconductor device
    Patent number: 9391449
    Abstract: Of a wireless communication system, an RF tag which can operate normally even when a communication distance is extremely short, like the case where the RF tag is in contact with a reader/writer, whereby the reliability is improved. The RF tag which communicates data by wireless communication includes a comparison circuit which compares electric power supplied from outside with reference electric power and a protection circuit portion which is operated when the electric power supplied from outside is higher than the reference electric power in the comparison circuit.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: July 12, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Asami Tadokoro
  • Semiconductor device and communication system
    Patent number: 9384439
    Abstract: It is an object of the present invention to provide a semiconductor device in which a sophisticated integrated circuit using a polycrystalline semiconductor is formed over a substrate which is weak with heat such as a plastic substrate or a plastic film substrate and a semiconductor device which transmits/receives power or a signal without wires, and a communication system thereof. One feature of the invention is that a semiconductor device, specifically, a processor, in which a sophisticated integrated circuit is fixed to a plastic substrate which is weak with heat by a stripping method such as a stress peel of process method to transmit/receive power or a signal without wires, for example, with an antenna or a light receiving element.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: July 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato
  • System operations management apparatus, system operations management method and program storage medium
    Patent number: 9384079
    Abstract: In a system operations management apparatus, a burden to a system administrator when providing a decision criterion in detection of a failure in the future is reduced. The system operations management apparatus 1 includes a performance information accumulation unit 12, a model generation unit 30 and an analysis unit 31. The performance information accumulation unit 12 stores performance information including a plurality of types of performance values in a system in time series. The model generation unit 30 generates a correlation model including one or more correlations between the different types of performance values stored in the performance information accumulation unit 12 for each of a plurality of periods having one of a plurality of attributes.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: July 5, 2016
    Assignee: NEC CORPORATION
    Inventor: Kiyoshi Kato
  • Semiconductor device
    Patent number: 9373640
    Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: June 21, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Semiconductor device
    Patent number: 9373643
    Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: June 21, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Jun Koyama
  • SEMICONDUCTOR DEVICE, MEMORY DEVICE, AND ELECTRONIC DEVICE
    Publication number: 20160172010
    Abstract: To provide a small, highly reliable memory device with a large storage capacity. A semiconductor device includes a circuit for retaining data and a circuit for reading data. The circuit for retaining data includes a transistor and a capacitor. The circuit for reading data is configured to supply a potential to the circuit for retaining data and read a potential from the circuit for retaining data. The circuit for retaining data and the circuit for reading data are provided in different layers, so that the semiconductor device with a large storage capacity is manufactured.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 16, 2016
    Inventor: Kiyoshi KATO
  • SEMICONDUCTOR DEVICE
    Publication number: 20160163742
    Abstract: A semiconductor device includes an oxide layer, a source electrode layer in contact with the oxide layer, a first drain electrode layer in contact with the oxide layer, a second drain electrode layer in contact with the oxide layer, a gate insulating film in contact with the oxide layer, a first gate electrode layer overlapping with the source electrode layer and the first drain electrode layer and overlapping with a top surface of the oxide layer with the gate insulating film interposed therebetween, a second gate electrode layer overlapping with the source electrode layer and the second drain electrode layer and overlapping with the top surface of the oxide layer with the gate insulating film interposed therebetween, and a third gate electrode layer overlapping with a side surface of the oxide layer with the gate insulating film interposed therebetween.
    Type: Application
    Filed: February 5, 2016
    Publication date: June 9, 2016
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Kiyoshi KATO
  • SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF
    Publication number: 20160155480
    Abstract: A semiconductor device capable of inhibiting incorrect data readout is provided. In a memory cell including a first transistor, a second transistor, and a third transistor, the potential of a fourth wiring is set to GND when data is written, and the potential is set to VDD when data is read out, for example. Note that the potential of a third wiring is set to GND when data is written and when data is read out, for example. When data is read out, the first transistor is off, so that a first capacitor and a fourth capacitor are connected in series. The potential of a second electrode of the second capacitor increases in this state, and thus part of charges accumulated in the second capacitor transfers to the first capacitor, so that the potential of a node increases.
    Type: Application
    Filed: November 25, 2015
    Publication date: June 2, 2016
    Inventors: Hiroki INOUE, Kiyoshi KATO, Takanori MATSUZAKI