Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor includes an oxide over a first insulator, a second insulator over the oxide, a first conductor over the second insulator, a third insulator over the first conductor, a fourth insulator in contact with the second insulator, the first conductor, and the third insulator, and a fifth insulator in contact with the fourth insulator. The second transistor includes an oxide over the first insulator, a sixth insulator over the oxide, a second conductor over the sixth insulator, a seventh insulator over the second conductor, an eighth insulator in contact with the sixth insulator, the second conductor, and the seventh insulator, and a ninth insulator in contact with the eighth insulator. The first capacitor includes an oxide, a tenth insulator over the oxide, and a third conductor over the tenth insulator.

Abstract: A semiconductor device with a large storage capacity per unit area is provided. A semiconductor device includes a memory cell. The memory cell includes a first conductor; a first insulator over the first conductor; a first oxide over the first insulator and including a first region, a second region, and a third region positioned between the first region and the second region; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator positioned in contact with a side surface of the first region; and a second oxide positioned on the side surface of the first region, with the third insulator therebetween. The first region includes a region overlapping the first conductor. The third region includes a region overlapped by the second conductor. The first region and the second region have a lower resistance than the third region.

Abstract: Provided is a structure which is capable of central control of an electric device and a sensor device and a structure which can reduce power consumption of an electric device and a sensor device. A central control system includes at least a central control device, an output unit, and an electric device or a sensor device. The central control device performs arithmetic processing on information transmitted from the electric device or the sensor device and makes the output unit output information obtained by the arithmetic processing. It is possible to know the state of the electric device or the sensor device even apart from the electric device or the sensor device. The electric device or the sensor device includes a transistor which includes an activation layer using a semiconductor with the band gap wider than that of single crystal silicon.

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

Abstract: Accuracy of risks defined for abnormalities that might occur in a system is improved. The risk determination device 100 includes a classification unit 114 and a determination unit 115. The classification unit 114 classifies abnormal patterns 133, each representing a relationship among metrics at a time of abnormality detection in a system, into groups 134 based on a similarity between the abnormal patterns. The determination unit 115 determines, based on the number of abnormal patterns 133 classified into each of the groups 134, likelihood of an abnormality of the corresponding group 134.

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

Abstract: A semiconductor device that can retain data for a long time is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor contains an oxide semiconductor in a channel formation region. The second transistor includes a first gate and a second gate. A gate of the first transistor is connected to a first electrode of the first transistor. The first electrode of the first transistor is connected to the second gate. A negative potential is applied to a second electrode of the first transistor. The first electrode and the second electrode of the first transistor include a first end portion and a second end portion, respectively. The first end portion and the second end portion face each other. The first end portion includes a first arc and the second end portion includes a second arc when seen from the top. The radius of curvature of the second arc is larger than that of the first arc.

Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

Abstract: A semiconductor device capable of holding data for a long time is provided. The semiconductor device includes a first transistor, a second transistor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first semiconductor provided therebetween. The second transistor includes a second semiconductor in a channel formation region. A first terminal of the second transistor is electrically connected to a gate of the second transistor and the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential. The second semiconductor has a wider bandgap than the first semiconductor.

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

Abstract: In a system operations management apparatus, a burden to a system administrator when providing a decision criterion in detection of a failure in the future is reduced. The system operations management apparatus 1 includes a performance information accumulation unit 12, a model generation unit 30 and an analysis unit 31. The performance information accumulation unit 12 stores performance information including a plurality of types of performance values in a system in time series. The model generation unit 30 generates a correlation model including one or more correlations between the different types of performance values stored in the performance information accumulation unit 12 for each of a plurality of periods having one of a plurality of attributes.

Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.

Abstract: A novel semiconductor device or memory device is provided. Alternatively, a semiconductor device or memory device in which storage capacity per unit area is large is provided. The semiconductor device includes a sense amplifier provided to a semiconductor substrate and a memory cell provided over the sense amplifier. The sense amplifier includes a first transistor. The memory cell includes a capacitor over the semiconductor substrate, a second transistor provided over the capacitor, a conductor, and a groove portion. The capacitor includes a first electrode and a second electrode. The first electrode is formed along the groove portion. The second electrode has a region facing the first electrode in the groove portion. The second transistor includes an oxide semiconductor. One of a source and a drain of the second transistor is electrically connected to the second electrode through the conductor.

Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

Abstract: It is an object of the present invention to provide a semiconductor device in which a sophisticated integrated circuit using a polycrystalline semiconductor is formed over a substrate which is weak with heat such as a plastic substrate or a plastic film substrate and a semiconductor device which transmits/receives power or a signal without wires, and a communication system thereof. One feature of the invention is that a semiconductor device, specifically, a processor, in which a sophisticated integrated circuit is fixed to a plastic substrate which is weak with heat by a stripping method such as a stress peel of process method to transmit/receive power or a signal without wires, for example, with an antenna or a light receiving element.