Patents by Inventor Kiyoshi Kawabata

Kiyoshi Kawabata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240101307
    Abstract: A replacement lead case includes a case body that forms an inner space surrounded by a rear surface plate and right and left leg plates as a replacement lead accommodation room and has a lid body on the tip end thereof and a case part on a rear part thereof via a bendable thin part provided on the rear surface plate, and a cover member that has a U-shaped cross-section orthogonal to a longitudinal direction molded by a front surface plate and right and left outer leg plates covers the replacement lead accommodation room on a case body with the front surface plate and slidably supports the case body in the longitudinal direction with the leg plates positioned on the inside of the outer leg plates. A rail-shaped guide is formed on the lid body along the longitudinal direction, and the cover member includes a slider that contacts the guide.
    Type: Application
    Filed: December 16, 2021
    Publication date: March 28, 2024
    Applicant: MITSUBISHI PENCIL COMPANY, LIMITED
    Inventors: Mitsuhiro KAWABATA, Kyoichiro NAKAMURA, Kiyoshi FUJISAWA
  • Patent number: 8269295
    Abstract: There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length smaller than the half of the maximum length in the direction perpendicular to the easy-axis, and on the one side and on the other side of the primary straight line respectively, the planar shape has a first part situated over a length in the direction perpendicular to the easy-axis, and a second part situated over a length smaller than the length in the direction perpendicular to the easy-axis. The outer edge of the first part includes only a smooth curve convex outwardly of the outer edge.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: September 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Takenaga, Takeharu Kuroiwa, Hiroshi Takada, Shuichi Ueno, Kiyoshi Kawabata
  • Patent number: 8013407
    Abstract: There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length smaller than the half of the maximum length in the direction perpendicular to the easy-axis, and on the one side and on the other side of the primary straight line respectively, the planar shape has a first part situated over a length in the direction perpendicular to the easy-axis, and a second part situated over a length smaller than the length in the direction perpendicular to the easy-axis. The outer edge of the first part includes only a smooth curve convex outwardly of the outer edge.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: September 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Takenaga, Takeharu Kuroiwa, Hiroshi Takada, Shuichi Ueno, Kiyoshi Kawabata
  • Publication number: 20110193185
    Abstract: There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length smaller than the half of the maximum length in the direction perpendicular to the easy-axis, and on the one side and on the other side of the primary straight line respectively, the planar shape has a first part situated over a length in the direction perpendicular to the easy-axis, and a second part situated over a length smaller than the length in the direction perpendicular to the easy-axis. The outer edge of the first part includes only a smooth curve convex outwardly of the outer edge.
    Type: Application
    Filed: April 18, 2011
    Publication date: August 11, 2011
    Applicant: RENESAS ELECTRONICS CORPORTION
    Inventors: Takashi Takenaga, Takeharu Kuroiwa, Hiroshi Takada, Shuichi Ueno, Kiyoshi Kawabata
  • Patent number: 7890148
    Abstract: A mobile station for a CDMA communication system which comprises a transmitting section that transmits a location registration request signal to a base station, and a receiving section that receives an acknowledge signal transmitted from the base station after the location registration request signal from the transmitting section is received by the base station. A control section prohibits the power supply to the receiving section for a predetermined period of time if the acknowledge signal from the base station is not received within a predetermined period of time after the location registration request signal has been transmitted.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: February 15, 2011
    Assignee: Fujitsu Toshiba Mobile Communications Limited
    Inventors: Masayuki Enoki, Kiyoshi Kawabata
  • Patent number: 7701743
    Abstract: An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: April 20, 2010
    Assignee: Rising Silicon, Inc.
    Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
  • Publication number: 20090250776
    Abstract: There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length smaller than the half of the maximum length in the direction perpendicular to the easy-axis, and on the one side and on the other side of the primary straight line respectively, the planar shape has a first part situated over a length in the direction perpendicular to the easy-axis, and a second part situated over a length smaller than the length in the direction perpendicular to the easy-axis. The outer edge of the first part includes only a smooth curve convex outwardly of the outer edge.
    Type: Application
    Filed: March 6, 2009
    Publication date: October 8, 2009
    Inventors: Takashi Takenaga, Takeharu Kuroiwa, Hiroshi Takada, Shuichi Ueno, Kiyoshi Kawabata
  • Publication number: 20080303175
    Abstract: An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate.
    Type: Application
    Filed: August 7, 2008
    Publication date: December 11, 2008
    Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
  • Patent number: 7425763
    Abstract: An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: September 16, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
  • Publication number: 20070263555
    Abstract: A mobile station for a CDMA communication system which comprises a transmitting section that transmits a location registration request signal to a base station, and a receiving section that receives an acknowledge signal transmitted from the base station after the location registration request signal from the transmitting section is received by the base station. A control section prohibits the power supply to the receiving section for a predetermined period of time if the acknowledge signal from the base station is not received within a predetermined period of time after the location registration request signal has been transmitted.
    Type: Application
    Filed: July 20, 2007
    Publication date: November 15, 2007
    Inventors: Masayuki Enoki, Kiyoshi Kawabata
  • Patent number: 7289832
    Abstract: A mobile station for a CDMA communication system which comprises a transmitting section that transmits a location registration request signal to a base station, and a receiving section that receives an acknowledge signal transmitted from the base station after the location registration request signal from the transmitting section is received by the base station. A control section prohibits the power supply to the receiving section for a predetermined period of time if the acknowledge signal from the base station is not received within a predetermined period of time after the location registration request signal has been transmitted.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: October 30, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Enoki, Kiyoshi Kawabata
  • Publication number: 20070158814
    Abstract: An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate.
    Type: Application
    Filed: March 7, 2007
    Publication date: July 12, 2007
    Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
  • Patent number: 7233534
    Abstract: An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: June 19, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
  • Patent number: 7120069
    Abstract: An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: October 10, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
  • Publication number: 20050248017
    Abstract: An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.
    Type: Application
    Filed: July 14, 2005
    Publication date: November 10, 2005
    Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
  • Publication number: 20040164324
    Abstract: An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.
    Type: Application
    Filed: February 26, 2004
    Publication date: August 26, 2004
    Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
  • Patent number: 6728904
    Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: April 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
  • Publication number: 20030156441
    Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.
    Type: Application
    Filed: February 24, 2003
    Publication date: August 21, 2003
    Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
  • Patent number: 6584004
    Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: June 24, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
  • Publication number: 20010010064
    Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.
    Type: Application
    Filed: February 28, 2001
    Publication date: July 26, 2001
    Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima