Patents by Inventor Kiyoshi Matsunaga

Kiyoshi Matsunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8349656
    Abstract: In order to remove plating burrs generated in etching step, there is provided a manufacturing method of semiconductor devices on each of unit leadframes in a leadframe material in which a plurality of the unit leadframes are arranged in plural rows or a single row, wherein at least two types of plating burr removals are conducted after a half-etching is performed onto a front surface side of the leadframe material, using a first plating layer as resist film.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: January 8, 2013
    Assignee: Mitsui High-Tec, Inc.
    Inventors: Yusuke Etou, Naoki Fukami, Kiyoshi Matsunaga
  • Patent number: 8159055
    Abstract: A semiconductor device includes a semiconductor element; a group of back-inner terminals coupled with the semiconductor element through bonding wires and arranged in an area array shape so as to be exposed inside of the bottom; a group of back-outer terminals arranged outside the group of back-inner terminals; a group of front-outer terminals located immediately above the back-outer terminals to be exposed from the front surface, which are electrically coupled with the back-outer terminals located immediately therebelow through coupling conductors, respectively; and a sealing resin which seals the semiconductor element and bonding wires and non-exposed portions of said back-inner terminals, back-outer terminals and front-outer terminals. On at least the respective terminal faces of said back-inner terminals, back-outer terminals and front-outer terminals, noble-metal plated layers are formed.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: April 17, 2012
    Assignee: Mitsui High-Tec, Inc.
    Inventors: Kiyoshi Matsunaga, Takao Shioyama, Tetsuyuki Hirashima
  • Publication number: 20110059577
    Abstract: In order to remove plating burrs generated in etching step, there is provided a manufacturing method of semiconductor devices on each of unit leadframes in a leadframe material in which a plurality of the unit leadframes are arranged in plural rows or a single row, wherein at least two types of plating burr removals are conducted after a half-etching is performed onto a front surface side of the leadframe material, using a first plating layer as resist film.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 10, 2011
    Applicant: MITSUI HIGH-TECH, INC.
    Inventors: Yusuke ETOU, Naoki FUKAMI, Kiyoshi MATSUNAGA
  • Patent number: 7665205
    Abstract: Disclosed are a method for manufacturing a laminated lead frame and a laminated lead frame manufactured thereby, wherein lead frame single plates to be laminated one on top of the other can be reliably bonded together with a relatively light load. Under the method for manufacturing a laminated lead frame by means of stacking and bonding lead frame single plates 10 and 11, each of which has been processed into a predetermined shape, a plurality of protuberance sections 12 are formed in at least one of mutually-opposing surfaces of the lead frame single plates 10 and 11 that vertically pair up with each other. The mutually-opposing lead frame single plates 11, 12 are bonded together via the protuberance sections 12.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: February 23, 2010
    Assignee: Mitsui High-Tec, Inc.
    Inventors: Kiyoshi Matsunaga, Chikaya Mimura, Takao Shioyama
  • Patent number: 7411222
    Abstract: A package for light emitting element including a package main body 1 having a bottom face 7a on which a light emitting element 2 is arranged, and a concave portion 7 which is formed in an inverted truncated cone shape by an inner wall face 7b intersecting with the bottom face 7a with a predetermined angle, and a translucent member 6 filled in the concave portion 7 of the package main body 1, the angle between the inner wall face 7b composing the concave portion 7 and the bottom face 7a is selected within ±15° of the incident critical angle in which a direct light radiated from the light emitting element 2 undergoes total reflection at the interface between the translucent member 6 and air.
    Type: Grant
    Filed: November 11, 2004
    Date of Patent: August 12, 2008
    Assignee: Harison Toshiba Lighting Corporation
    Inventors: Junichi Kinoshita, Tsuneo Nakayama, Takao Mizukami, Yuji Wagatsuma, Kiyoshi Matsunaga, Naoki Matsuoka, Norihiko Ochi
  • Publication number: 20080067649
    Abstract: A semiconductor device includes a semiconductor element; a group of back-inner terminals coupled with the semiconductor element through bonding wires and arranged in an area array shape so as to be exposed inside of the bottom; a group of back-outer terminals arranged outside the group of back-inner terminals; a group of front-outer terminals located immediately above the back-outer terminals to be exposed from the front surface, which are electrically coupled with the back-outer terminals located immediately therebelow through coupling conductors, respectively; and a sealing resin which seals the semiconductor element and bonding wires and non-exposed portions of said back-inner terminals, back-outer terminals and front-outer terminals. On at least the respective terminal faces of said back-inner terminals, back-outer terminals and front-outer terminals, noble-metal plated layers are formed.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 20, 2008
    Applicant: MITSUI HIGH-TEC, INC.
    Inventors: Kiyoshi MATSUNAGA, Takao SHIOYAMA, Tetsuyuki HIRASHIMA
  • Publication number: 20070119050
    Abstract: Disclosed are a method for manufacturing a laminated lead frame and a laminated lead frame manufactured thereby, wherein lead frame single plates to be laminated one on top of the other can be reliably bonded together with a relatively light load. Under the method for manufacturing a laminated lead frame by means of stacking and bonding lead frame single plates 10 and 11, each of which has been processed into a predetermined shape, a plurality of protuberance sections 12 are formed in at least one of mutually-opposing surfaces of the lead frame single plates 10 and 11 that vertically pair up with each other. The mutually-opposing lead frame single plates 11, 12 are bonded together via the protuberance sections 12.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 31, 2007
    Inventors: Kiyoshi Matsunaga, Chikaya Mimura, Takao Shioyama