Abstract: A circuit includes a control flip-flop inputting a scan control signal and a scan path chain formed of scan storage elements serially connected. The scan path chain performs a shift operation as a first mode when the control flip-flop outputs a first status value, and performs a normal operation as a second mode when the control flip-flop outputs a second status value. When the scan control signal is switched from the first status value to the second status value, the control flip-flop outputs the second status value to the scan storage elements in synchronization with a first clock pulse, after the switching, of a clock provided to the scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control flip-flop outputs the first status value to the scan storage elements at a timing of the scan control signal switching.

Abstract: A semiconductor integrated circuit, includes a control flip-flop for inputting a scan control signal and a scan path chain formed of a plurality of scan storage elements serially connected to each other. The scan path chain performs a shift operation as a first mode when an output of the control flip-flop is a first status value, and performs a normal operation as a second mode when an output of the control flip-flop is a second status value. When the scan control signal is switched from the first status value to the second status value, the control flip-flop outputs the second status value to the plurality of scan storage elements in synchronization with a first clock pulse, after the switching, of a clock provided to the plurality of scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control flip-flop outputs the first status value to the plurality of scan storage elements at a timing of the scan control signal switching.

Abstract: A scan test circuit in the present invention includes a control FF for inputting a control signal, and a scan path chain configured of scan storage elements to operate in a shift operation mode when an output of the control FF is a first status value, and in a normal operation mode when the output is a second status value. When the control signal is switched from the first status value to the second status value, the control FF outputs the second status value to multiple scan storage elements synchronously with a first clock pulse, after the switching, of a clock provided to multiple scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control FF outputs the first status value to multiple scan storage elements at a timing of the control signal switching.

Abstract: A scan test circuit in the present invention includes a control FF for inputting a control signal, and a scan path chain configured of scan storage elements to operate in a, shift operation mode when an output of the control FF is a first status value, and in a normal operation mode when the output is a second status value. When the control signal is switched from the first status value to the second status value, the control FF outputs the second status value to multiple scan storage elements synchronously with a first clock pulse, after the switching, of a clock provided to multiple scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control FF outputs the first status value to multiple scan storage elements at a timing of the control signal switching.

Abstract: A digital PLL circuit includes a sampler which samples a burst data signal depending on N phase clock signals to produce N phase sampled data signals. Based on the N phase sampled data signals, an edge phase detector detects edge information and a duty detector detects duty information signals in synchronization with the reference signal. A selector selects an optimal sampled data signal from the N phase sampled data signals depending on the edge information and the duty information, and a retiming section retimes the sampled data signal selected in synchronization with the reference signal.