Patents by Inventor Kiyoshi Muratake

Kiyoshi Muratake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6143590
    Abstract: A method of making a semiconductor device including: a ceramic base board formed of AlN; a CPU chip and a CMU chip which are flip-chip bonded on a circuit board which includes the ceramic base board; SRAM chips which are die-bonded to the lower major surface of the circuit board; first heat conductive blocks adhesively attached to the CPU chip and the CMU chip; second heat conductive blocks adhesively attached to the upper major surface of the AlN ceramic base board; a resin package; and a heat sink which, adhesively attached on the upper major surface of the resin package, is in close contact with the first heat conductive blocks and the second heat conductive blocks. The heat generated by the CPU chip and the CMU chip is transferred to the heat sink via the first heat conductive blocks and is radiated from the heat sink.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: November 7, 2000
    Assignee: Fujitsu Limited
    Inventors: Ken'ichi Ohki, Kiyoshi Muratake, Hidetoshi Inoue, Takehisa Tsujimura
  • Patent number: 5886408
    Abstract: A semiconductor device including: a ceramic base board formed of A1N; a CPU chip and a CMU chip which are flip-chip bonded on a circuit board which includes the ceramic base board; SRAM chips which are die-bonded to the lower major surface of the circuit board; first heat conductive blocks adhesively attached to the CPU chip and the CMU chip; second heat conductive blocks adhesively attached to the upper major surface of the A1N ceramic base board; a resin package; and a heat sink which, adhesively attached on the upper major surface of the resin package, is in close contact with the first heat conductive blocks and the second heat conductive blocks. The heat generated by the CPU chip and the CMU chip is transferred to the heat sink via the first heat conductive blocks and is radiated from the heat sink. The heat generated by the SRAM chips is transferred to the heat sink via the A1N ceramic base board and the second heat conductive blocks and is radiated from the heat sink.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: March 23, 1999
    Assignee: Fujitsu Limited
    Inventors: Ken'ichi Ohki, Kiyoshi Muratake, Hidetoshi Inoue, Takehisa Tsujimura
  • Patent number: 4724472
    Abstract: A semiconductor device to be mounted on a circuit board, including a semiconductor chip, a package for mounting the semiconductor chip, a plurality of conductor pads provided on the outer surface of the package, and a plurality of conductor pins, connected to the conductor pads in a substantially vertical contact condition, for connecting to the circuit board in accordance with a contacting condition.
    Type: Grant
    Filed: January 14, 1987
    Date of Patent: February 9, 1988
    Assignee: Fujitsu Limited
    Inventors: Masahiro Sugimoto, Tetsushi Wakabayashi, Kiyoshi Muratake
  • Patent number: 4688077
    Abstract: A semiconductor device having a semiconductor package and a radiator. The semiconductor package houses a semiconductor chip therein. The radiator includes a pillar which has a plurality of fins thereon. One end of the pillar is bonded to the semiconductor package. A hole is formed in the other end of the pillar and extends the longitudinal direction of the pillar.
    Type: Grant
    Filed: January 28, 1986
    Date of Patent: August 18, 1987
    Assignee: Fujitsu Limited
    Inventors: Tetsushi Wakabayashi, Masahiro Sugimoto, Kiyoshi Muratake
  • Patent number: 4598307
    Abstract: In order to protect ICs from noise it is necessary to mount a bypass capacitor as close as possible to the IC die or chip. The package must seal the die from the environment, but there are marginal spaces at the ends of a dual in line type package (DIP type package) which are not needed for the sealing function. An opening is made in the lid of the package at such a marginal area, and a chip capacitor is mounted in the opening. An additional post is provided on the lead frame. A portion of this additional post and a portion of another lead provided by the frame are exposed through the opening in the lid. The chip capacitor is soldered to the exposed portions to mechanically and electrically connect the capacitor. The additional post is scored at the edge of the package to permit easy removal of the portion thereof that would otherwise extend outside the package.
    Type: Grant
    Filed: September 7, 1983
    Date of Patent: July 1, 1986
    Assignee: Fujitsu Limited
    Inventors: Tetsushi Wakabayashi, Kiyoshi Muratake