Abstract: The memory power consumption is reduced more than in the past by performing a power control suitably for a nonvolatile memory. A memory control circuit is provided with a first register group for a CPU to perform separately initial setting of the operation mode (power OFF, standby, and power ON) of plural banks included in a nonvolatile memory, for every task of a program executed by the CPU, and an access determination unit which determines a bank to which an access from the CPU takes place, on the basis of the access address for instruction fetching and the kind of the fetched instruction. The memory control circuit switches the operation mode of each of the banks on the basis of the setting value of the first register group, and the determination result of the access determination unit.

Abstract: A program counter (12) updates an address by adding a first value or a second value. A code select circuit (14) selects, in accordance with the address of the program counter (12), one of an insert code retained in an insert code register set block (17) and corresponding to the address specified by the program counter (12), and an original code stored in a flash control code ROM (13) and having the address specified by the program counter (12). An instruction execution unit (15) executes the selected code. At least one of a plurality of original codes and the insert code is a multicycle instruction. The program counter (14) stops update of the address when the multicycle instruction is executed.

Abstract: The memory power consumption is reduced more than in the past by performing a power control suitably for a nonvolatile memory. A memory control circuit is provided with a first register group for a CPU to perform separately initial setting of the operation mode (power OFF, standby, and power ON) of plural banks included in a nonvolatile memory, for every task of a program executed by the CPU, and an access determination unit which determines a bank to which an access from the CPU takes place, on the basis of the access address for instruction fetching and the kind of the fetched instruction. The memory control circuit switches the operation mode of each of the banks on the basis of the setting value of the first register group, and the determination result of the access determination unit.

Abstract: A house code assigning device includes a communication unit for sending a command for requesting transmission of a house code to electronic equipment included in a system and for receiving a house code from the electronic equipment, a verification unit for verifying whether or not a house code received by the communication unit is correct and for outputting a verification result showing whether or not the house code received by the communication unit is correct, and a display control unit for controlling a light emitting unit according to the verification result from the verification unit.

Abstract: An angular difference detector detects an angular variation according to respective signs of current xy coordinate values supplied from an FFT calculation unit and respective signs of preceding xy coordinate values. An angle calculation unit calculates an angle value of a frequency component according to respective absolute values of xy coordinate values supplied from the FFT calculation unit. Another angular difference detector classifies a difference between a current angle value and a preceding angle value supplied from a subtractor as one of a plurality of angle regions to detect an angular difference. A demapper performs demapping according to a sum of the angular variation supplied from the angular difference detector and the angular difference supplied from that another angular difference detector.

Abstract: An angular difference detector detects an angular variation according to respective signs of current xy coordinate values supplied from an FFT calculation unit and respective signs of preceding xy coordinate values. An angle calculation unit calculates an angle value of a frequency component according to respective absolute values of xy coordinate values supplied from the FFT calculation unit. Another angular difference detector classifies a difference between a current angle value and a preceding angle value supplied from a subtractor as one of a plurality of angle regions to detect an angular difference. A demapper performs demapping according to a sum of the angular variation supplied from the angular difference detector and the angular difference supplied from that another angular difference detector.

Abstract: A microprocessor having a saturation operation unit comprising a decoder 220 for decoding a 4-bit saturation operation bit length data item into a 16-bit value, a decoder 221 for decoding a 5-bit saturation operation bit length data item into 1 to a 32-bit value, selectors 236, 237, 238, 239 and an operation unit 250 for outputting values stored in the decoder 220 and 221 or values obtained by inverting the values, per bit, stored in the decoder 220 and 221 when a target saturation operation value is over a saturated value detected by using selectors 234, 235 and operation units 226 and 227.