Patents by Inventor Kiyoshi Nakashima

Kiyoshi Nakashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7571432
    Abstract: A compiler 58, which is a compiler that realizes program development in a fewer man hours, translates a source program 72 written in a high-level language into a machine language program. This compiler 58 is comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unit 76 that parses the source program 72; an intermediate code conversion unit 78 that converts the source program 72 into intermediate codes based on a result of the parsing performed by the parser unit 76; an optimization unit 68 that optimizes the intermediate codes according to the directive; and a code generation unit 90 that converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: August 4, 2009
    Assignee: Panasonic Corporation
    Inventors: Taketo Heishi, Hajime Ogawa, Yasuhiro Yamamoto, Kyoko Hattori, Shohei Michimoto, Kenji Hattori, Hirotetsu Tomita, Teruo Kawabata, Kiyoshi Nakashima
  • Patent number: 7424578
    Abstract: A compiler apparatus for a computer system capable of improving the hit rate of a cache memory, which includes a prefetch target extraction device, a thread activation process insertion device, and a thread process creation device. The compiler apparatus creates threads for performing prefetch and prepurge. Prefetch and prepurge threads created by this compiler apparatus perform prefetch and prepurge in parallel with the operation of the main program, by taking into consideration program priorities and the usage ratio of the cache memory.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: September 9, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Nakashima, Taketo Heishi, Shohei Michimoto
  • Publication number: 20050144420
    Abstract: The data processing apparatus capable of efficiently using a cache memory includes: a cache memory 28 and a memory 30 that stores an instruction or data in each area specified by a physical address; an arithmetic processing unit 22 that outputs a logical address including the physical address and process determining data indicating a prescribed process, obtains the instruction or the data corresponding to the physical address included in the logical address, and execute the instruction; an address conversion unit 26 that converts the logical address outputted by the arithmetic processing unit 22 into the physical address. The data processing apparatus reads the instruction or the data stored in areas specified by the physical address, in the cache memory 28 and the memory 30, and executes a prescribed process based on the process determining data.
    Type: Application
    Filed: November 24, 2004
    Publication date: June 30, 2005
    Inventors: Shohei Michimoto, Hajime Ogawa, Taketo Heishi, Kiyoshi Nakashima, Hazuki Okabayashi, Ryuta Nakanishi
  • Publication number: 20050086653
    Abstract: A compiler 58, which is a compiler that realizes program development in a fewer man hours, translates a source program 72 written in a high-level language into a machine language program. This compiler 58 is comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unit 76 that parses the source program 72; an intermediate code conversion unit 78 that converts the source program 72 into intermediate codes based on a result of the parsing performed by the parser unit 76; an optimization unit 68 that optimizes the intermediate codes according to the directive; and a code generation unit 90 that converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.
    Type: Application
    Filed: September 21, 2004
    Publication date: April 21, 2005
    Inventors: Taketo Heishi, Hajime Ogawa, Yasuhiro Yamamoto, Kyoko Hattori, Shohei Michimoto, Kenji Hattori, Hirotetsu Tomita, Teruo Kawabata, Kiyoshi Nakashima
  • Publication number: 20050071572
    Abstract: A complier apparatus for a computer system that is capable of improving the hit rate of a cache memory is comprised of a prefetch target extraction device, a thread activation process insertion device, and a thread process creation device, and creates threads for performing prefetch and prepurge. Prefetch and prepurge threads created by this compiler apparatus perform prefetch and prepurge in parallel with the operation of the main program, by taking into consideration program priorities and the usage ratio of the cache memory.
    Type: Application
    Filed: July 8, 2004
    Publication date: March 31, 2005
    Inventors: Kiyoshi Nakashima, Taketo Heishi, Shohei Michimoto
  • Publication number: 20030159424
    Abstract: A thread breakage preventing apparatus includes a tension relieving unit disposed on a running path of a yarn and serving to positively feed the yarn to a downstream side in a feeding amount corresponding to a tension of the yarn when the tension exceeds a preset tension. A part of the tension relieving unit is a rotational roller to be rotated at a constant rotating speed and serves to instantaneously increase and decrease the feeding amount of the yarn based on a behavior of the yarn corresponding to an increase and decrease in the tension of the yarn.
    Type: Application
    Filed: February 18, 2003
    Publication date: August 28, 2003
    Inventors: Kiyoshi Nakashima, Yutaka Takahama
  • Patent number: 5141795
    Abstract: A laminate film for forming a tightly sealed bag that can be opened easily by tearing at an edge thereof. The film is a laminate of a substrate layer and a heat seal layer, the substrate layer having a multiplicity of through cuts formed therein, said through cuts being partially or wholly filled by the heat seal layer material.
    Type: Grant
    Filed: July 15, 1991
    Date of Patent: August 25, 1992
    Assignee: Asahi Chemical Polyflex Ltd.
    Inventors: Hisao Kai, Kiyoshi Nakashima
  • Patent number: 5038547
    Abstract: A process for producing a tightly sealed bag that can be easily opened by tearing at an edge thereof. According to the process a multiplicity of through cuts are formed along a line in a laminate film having at least one substrate layer and at least one heat seal layer. The laminate film is formed into an open bag with the line of through cuts provided along an edge to be sealed of the bag and edges of the open bag are heat sealed to form a sealed bag. In an alternative embodiment of the process, a multiplicity of through cuts are formed along a line in a substrate film and a heat seal film is laminated to the substrate film provided with the through cuts to form a laminate film prior to forming the sealed bag.
    Type: Grant
    Filed: October 6, 1989
    Date of Patent: August 13, 1991
    Assignee: Asahi Chemical Polyflex, Ltd.
    Inventors: Hisao Kai, Kiyoshi Nakashima
  • Patent number: 4977807
    Abstract: A device for forming slits, or through cuts, in a plastic film. The device is a disc having a circumferential surface and pseudotriangular slender cutting edges consisting of protrusions aligned linearly in a plurality of straight rows extending around the entire circumferential surface, the protrusions extending outwardly from said circumferential surface at angle of at least 60.degree. and no greater than 100.degree..
    Type: Grant
    Filed: October 6, 1989
    Date of Patent: December 18, 1990
    Assignee: Asahi Chemical Polyflex Ltd.
    Inventors: Hisao Kai, Kiyoshi Nakashima
  • Patent number: 4919272
    Abstract: This invention provides an easily openable tightly sealed plastic bag which is formed of a film containing at least a substrate layer and a heat seal layer and is possessed of a sealed part whose substrate layer contains a multiplicity of through cuts, these cuts being formed substantially on the edge lines and partly or wholly closed with the heat seal layer. This tightly sealed bag safely retains the practical strength normally expected of any bag and avoids accidentally sustaining rupture while the bag is being transported or handled and yet permits itself to be opened with the force of finger tips. This invention manifests its utility particularly in a tightly sealed bag which is formed of a substrate of high strength and high barrier property. This invention further provides a method suitable for the production of the tightly sealed bag described above and a device to be used in working the method.
    Type: Grant
    Filed: October 12, 1988
    Date of Patent: April 24, 1990
    Assignee: Asahi Chemical Polyflex
    Inventors: Hisao Kai, Kiyoshi Nakashima